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Showing papers on "Field-effect transistor published in 1998"


Journal ArticleDOI
01 May 1998-Nature
TL;DR: In this paper, the fabrication of a three-terminal switching device at the level of a single molecule represents an important step towards molecular electronics and has attracted much interest, particularly because it could lead to new miniaturization strategies in the electronics and computer industry.
Abstract: The use of individual molecules as functional electronic devices was first proposed in the 1970s (ref 1) Since then, molecular electronics2,3 has attracted much interest, particularly because it could lead to conceptually new miniaturization strategies in the electronics and computer industry The realization of single-molecule devices has remained challenging, largely owing to difficulties in achieving electrical contact to individual molecules Recent advances in nanotechnology, however, have resulted in electrical measurements on single molecules4,5,6,7 Here we report the fabrication of a field-effect transistor—a three-terminal switching device—that consists of one semiconducting8,9,10 single-wall carbon nanotube11,12 connected to two metal electrodes By applying a voltage to a gate electrode, the nanotube can be switched from a conducting to an insulating state We have previously reported5 similar behaviour for a metallic single-wall carbon nanotube operated at extremely low temperatures The present device, in contrast, operates at room temperature, thereby meeting an important requirement for potential practical applications Electrical measurements on the nanotube transistor indicate that its operation characteristics can be qualitatively described by the semiclassical band-bending models currently used for traditional semiconductor devices The fabrication of the three-terminal switching device at the level of a single molecule represents an important step towards molecular electronics

5,258 citations


Journal ArticleDOI
TL;DR: In this article, the authors fabricated field effect transistors based on individual single and multi-wall carbon nanotubes and analyzed their performance, showing that structural deformations can make them operate as field-effect transistors.
Abstract: We fabricated field-effect transistors based on individual single- and multi-wall carbon nanotubes and analyzed their performance. Transport through the nanotubes is dominated by holes and, at room temperature, it appears to be diffusive rather than ballistic. By varying the gate voltage, we successfully modulated the conductance of a single-wall device by more than 5 orders of magnitude. Multi-wall nanotubes show typically no gate effect, but structural deformations—in our case a collapsed tube—can make them operate as field-effect transistors.

2,771 citations


Journal ArticleDOI
12 Jun 1998-Science
TL;DR: An all-polymer semiconductor integrated device is demonstrated with a high-mobility conjugated polymer field-effect transistor driving a polymer light-emitting diode (LED) of similar size, which represents a step toward all- polymer optoelectronic integrated circuits such as active-matrix polymer LED displays.
Abstract: An all-polymer semiconductor integrated device is demonstrated with a high-mobility conjugated polymer field-effect transistor (FET) driving a polymer light-emitting diode (LED) of similar size. The FET uses regioregular poly(hexylthiophene). Its performance approaches that of inorganic amorphous silicon FETs, with field-effect mobilities of 0.05 to 0.1 square centimeters per volt second and ON-OFF current ratios of >10 6 . The high mobility is attributed to the formation of extended polaron states as a result of local self-organization, in contrast to the variable-range hopping of self-localized polarons found in more disordered polymers. The FET-LED device represents a step toward all-polymer optoelectronic integrated circuits such as active-matrix polymer LED displays.

2,657 citations


Journal ArticleDOI
TL;DR: In this paper, the performance of organic field effect transistors (OFETs) is examined in terms of field effect mobility and on-off current ratio, and the most prominent fabrication techniques are described.
Abstract: Organic field-effect transistors (OFETs) were first described in 1987. Their characteristics have undergone spectacular improvements during the last two or three years. At the same time, several models have been developed to rationalize their operating mode. In this review, we examine the performance of OFETs as revealed by recently published data, mainly in terms of field-effect mobility and on–off current ratio. We compare the various compounds that have been used as the active component, and describe the most prominent fabrication techniques. Finally, we analyze the charge transport mechanisms in organic solids, and the resulting models of OFETs.

2,380 citations


Journal ArticleDOI
TL;DR: In this paper, the same type of studies have been carried out using metallophthalocyanine as the electroactive (semiconductive) part of a field effect transistor (FET).

418 citations


Journal ArticleDOI
TL;DR: In this paper, a single organic thin-film field effect transistor (FET) was integrated with an organic light-emitting diode to achieve a luminance of ∼2300cd/m2.
Abstract: The fabrication and characteristics of organic smart pixels are described. The smart pixel reported in this letter consists of a single organic thin-film field effect transistor (FET) monolithically integrated with an organic light-emitting diode. The FET active material is a regioregular polythiophene. The maximum optical power emitted by the smart pixel is about 300 nW/cm2 corresponding to a luminance of ∼2300 cd/m2.

372 citations



Journal ArticleDOI
TL;DR: In this article, two AB GaAs field effect transistor (FET) power amplifiers have been designed and fabricated in the 4.4-4.8 GHz range, and a dielectric PBG line was incorporated in the design to tune the second harmonic.
Abstract: Two class AB GaAs field-effect transistor (FET) power amplifiers have been designed and fabricated in the 4.4-4.8 GHz range. In the first case, a dielectric PBG line was incorporated in the design to tune the second harmonic. In the second case, a 50-/spl Omega/ line is used with no harmonic tuning. The PBG structure allows broad-band harmonic tuning and is inexpensive to fabricate. A 5% improvement in power-added efficiency was achieved at the design frequency of 4.5 GHz, in both simulation and measurement.

250 citations


Journal ArticleDOI
TL;DR: In this paper, a field effect transistor fabricated with an oxide channel has been shown to demonstrate switching characteristics similar to conventional silicon metal oxide field effect transistors, operating via a Mott metal-insulator transition induced by the gate field, and offers a potential technology alternative for the regime beyond silicon scaling limitations.
Abstract: A field effect transistor fabricated with an oxide channel has been shown to demonstrate switching characteristics similar to conventional silicon metal oxide field effect transistors. This device is believed to operate via a Mott metal-insulator transition induced by the gate field, and offers a potential technology alternative for the regime beyond silicon scaling limitations.

234 citations


Journal ArticleDOI
TL;DR: In this article, the effect of temperature on gate leakage was investigated and it was shown that gate leakage is significantly reduced at elevated temperature relative to a conventional metal-oxide-semiconductor field effect transistor (MOSFET) fabricated on the same GaN layer.
Abstract: Ga2O3(Gd2O3) was deposited on GaN for use as a gate dielectric in order to fabricate a depletion metal–oxide–semiconductor field-effect transistor (MOSFET). Analysis of the effect of temperature on the device shows that gate leakage is significantly reduced at elevated temperature relative to a conventional metal–semiconductor field-effect transistor fabricated on the same GaN layer. MOSFET device operation in fact improved upon heating to 400 °C. Modeling of the effect of temperature on contact resistance suggests that the improvement is due to a reduction in the parasitic resistances present in the device.

212 citations


Patent
09 Sep 1998
TL;DR: In this paper, a thin film field effect transistors and manufacturing method for the same are described, where the channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen.
Abstract: A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.

Journal ArticleDOI
TL;DR: In this article, an IGET consisting of molecular beam deposited α,ω-di-hexyl-hexathienylene (DH6T) as the semiconductor layer and different polymeric gate insulators was fabricated and tested.

Patent
07 Dec 1998
TL;DR: In this paper, a method for manufacturing a field effect transistor (100) includes forming source and drain regions (110, 112) in a semiconductor substrate (102) and forming a polysilicon gate (104) on a surface (106) adjacent to the source or drain regions.
Abstract: A method for manufacturing a field effect transistor (100) includes forming source and drain regions (110, 112) in a semiconductor substrate (102) and forming a polysilicon gate (104) on a surface (106) of the semiconductor substrate adjacent to the source and drain regions. A masking layer (136) is formed, covering substantially all the semiconductor substrate. Portions of the masking layer are then selectively removed to expose at least selected portions of the polysilicon gate. Selected portions of the polysilicon gate are partially etched. By selective electroless metal deposition, a metal layer (146) is formed on the etched selected portions of the polysilicon gate. In an alternative embodiment, the masking layer is removed before selective deposition of the electroless metal, so that electroless metal is simultaneously deposited on the polysilicon gate and the source region and the drain region.

Journal ArticleDOI
TL;DR: In this paper, the authors report on the recent developments and the performance level achieved in the strained-Si/SiGe material system, and propose possible future applications of strained Si and SiGe in high-performance SiGe CMOS technology.
Abstract: The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n- and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.

Patent
13 May 1998
TL;DR: In this article, a semiconductor circuit includes a substrate and a first well formed in the substrate, where a first group of field effect transistors is formed and has a first body.
Abstract: In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.

Journal ArticleDOI
TL;DR: In this paper, a static induction transistors (SITs) using copper phthalocyanine films and Al Schottky gate electrode are fabricated and the basic electrical characteristics are investigated.

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate the realization and functioning of a hybrid (organic/silicon) nanometer-size field effect transistor (nano-FET) having a gate length of 25 nm.
Abstract: We demonstrate the realization and functioning of a hybrid (organic/silicon) nanometer-size field effect transistor (nano-FET) having a gate length of 25 nm. The gate insulator is an organic self-assembled monolayer (SAM) of alkyltrichlorosilanes (∼2 nm thick). We have used densely packed SAMs with functionalized end groups (–CH3, –CH=CH2, –COOH) that all exhibit reduced leakage current density (10−8–10−5 A/cm2). This nano-FET is free of punchthrough down to 50 nm, and shows a good field effect behavior at 25 nm. This demonstrates the compatibility of these SAMs with semiconductor device processes and their wide capability for applications in nanometer-scale electronics.

Journal ArticleDOI
TL;DR: In this paper, the electron drift mobility in n-type AlGaN/GaN modulation-doped field effect transistors was analyzed and the two-dimensional character of the quantum confined carriers as well as spontaneous and piezoelectric electric field effects were fully taken into account.
Abstract: We present quantitative calculations of the electron drift mobility in wurtzite (WZ) and zincblende (ZB) structure n-type AlGaN/GaN modulation-doped field-effect transistors. The two-dimensional character of the quantum confined carriers as well as spontaneous and piezoelectric electric field effects are fully taken into account. For given doping concentration, we find that the internal electric fields lead to a much stronger carrier confinement and higher channel densities than in standard III–V materials. For high quality n-type heterostructures, we predict a room temperature mobility at high densities close to 2000 cm2/V s.

Patent
27 Jul 1998
TL;DR: In this article, a practical method of manufacturing an organic field-effect transistor was disclosed. But this method was based on applying the insulating layer having a thickness of 0.3 νm or less to a substantially planar electrode layer and satisfying the condition for voltage amplification at voltages well below 10 V.
Abstract: A practical method of manufacturing an organic field-effect transistor is disclosed. By applying the insulating layer having a thickness of 0.3 νm or less to a substantially planar electrode layer, an organic field-effect transistor can be made having a channel length down to 2 νm, satisfying the condition for voltage amplification at voltages well below 10 V, and having an on/off ratio of about 25.

Journal ArticleDOI
TL;DR: In this paper, a 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4HSiC substrate.
Abstract: A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET.

Patent
28 Sep 1998
TL;DR: In this article, a photoelectric conversion device has a plurality of pixel cells each of which includes a photo-electric conversion element, a field effect transistor having the gate area for storing signal charge generated by the photo conversion element and the source-drain path for outputting a signal corresponding to the signal charge stored in the gate.
Abstract: In a photoelectric conversion device having a plurality of pixel cells each of which includes a photoelectric conversion element, a field effect transistor having the gate area for storing signal charge generated by the photoelectric conversion element and the source-drain path for outputting a signal corresponding to the signal charge stored in the gate, a first power supply line for supplying electric power to the field effect transistor, and a first switch connected between the field effect transistor and the first power supply line, when a reset voltage for resetting the gate of the field effect transistor is Vsig0, a threshold voltage of the field effect transistor is Vth, current flowing through the field effect transistor is Ia, a voltage applied via the first power supply line is Vc1, and a series resistance of the first switch is Ron, each pixel cell is configured to satisfy a condition determined by Vc1−Ron×Ia>Vsig0−Vth.

Journal ArticleDOI
TL;DR: In this paper, the status of GaAs, SiC and GaN junction field effect transistors (JFETs) is reviewed with a focus on their application to high temperature and high power operation.
Abstract: The status of GaAs, SiC and GaN junction field effect transistors (JFETs) is reviewed with a focus on their application to high temperature and high power operation. The advantage of the JFET structure for this operation regime is detailed. Future directions for junction gated transistors are outlined.

Patent
Leonard Forbes1
24 Feb 1998
TL;DR: In this paper, an n-channel FET access transistor coupled between a memory cell and a data communication line is described, where the access transistors are fabricated as a single vertical pillar.
Abstract: A memory device is described which has an n-channel FET access transistor coupled between a memory cell and a data communication line. An NPN bipolar access transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar access transistor is described as coupled to a body of the n-channel access transistor to control threshold voltage variations of the n-channel FET access transistor. During operation the n-channel FET access transistor is used for writing data to a memory cell, while the NPN bipolar access transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.

Patent
10 Jun 1998
TL;DR: In this article, a MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbides substrate and having an n type drift layer and a p-type base layer.
Abstract: A MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and a p-type base layer. Preferably the base layer is formed by epitaxial growth and formed as a mesa. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also included are means for converting electron current flowing between the source and the drain into whole current for injection into the p-type base layer. Means for reducing field crowding associated with an insulating layer of said nMOSFET may also be provided.

Journal ArticleDOI
TL;DR: A quantum-dot transistor based on silicon self-assembled quantum dots has been fabricated by as mentioned in this paper, which shows staircases and oscillations in the drain current at room temperature, which are interpreted as due to single electron tunneling through the dots located in the shortest current path between the source and the drain electrodes.
Abstract: A quantum-dot transistor based on silicon self-assembled quantum dots has been fabricated The device shows staircases and oscillations in the drain current at room temperature These data are interpreted as due to single electron tunneling through the dots located in the shortest current path between the source and the drain electrodes The dot size calculated from the data is ∼7 nm, which is consistent with the size of the self-assembled dots incorporated in the transistor

Journal ArticleDOI
TL;DR: In this article, a double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon is presented, which has a thin channel and thick source/drain regions with a doublegate control.
Abstract: The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented.

Patent
15 May 1998
TL;DR: In this paper, a method for manufacturing an organic EL display including organic EL elements and an organic field effect transistors being integrated on a same substrate is disclosed. But this method requires the use of an organic gate insulating layer.
Abstract: A method for manufacturing an organic EL display including an organic EL elements and an organic field effect transistors being integrated on a same substrate is disclosed. A semitransparent electrode layer of the organic EL element and a gate electrode of the organic transistor are formed on a same transparent plastic substrate. An organic gate insulating layer is deposited on the gate electrode and an organic semiconductor layer is formed on the organic gate insulating layer. A source and drain electrodes is formed on the organic semiconductor layer. An organic EL layer is formed on the semitransparent electrode layer and a part of the drain electrode. The organic semiconductor layer can be made of a charge transfer complex or a thiophene derivative polymer. The resultant EL device is capable of mechanically bent, and then is readily adaptable for use in flexible displays.

Journal ArticleDOI
TL;DR: In this paper, low-frequency noise in the frequency region of 20 Hz to 20 kHz was investigated in AlGaN/GaN high electron mobility transistors (HEMTs) grown on SiC substrates.
Abstract: Low-frequency noise in the frequency region of 20 Hz to 20 kHz is investigated in AlGaN/GaN high electron mobility transistors (HEMTs) grown on SiC substrates. The noise spectra have the form of the 1/f (flicker) noise. The measured Hooge parameter is as low as 0.0001. This value is comparable with Hooge parameter values for commercial GaAs field effect transistors and approximately two orders of magnitude smaller than Hooge parameter value measured for AlGaN/GaN heterostructures grown on sapphire. The level of noise depends on the gate leakage current; the noise is much higher in devices with a high gate leakage current. The small measured values of the Hooge parameter are related to a smaller leakage current and to a better material quality of the devices on SiC substrates and to a high electron sheet density. The low levels of the 1/f noise in the AlGaN/GaN HEMTs on SiC substrates make them suitable for applications in communication systems.

Patent
Chunlin Liang1, Gang Bai1
30 Jun 1998
TL;DR: In this paper, a method for making a circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate.
Abstract: A method for making a circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

Patent
30 Mar 1998
TL;DR: In this article, a voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the input control signal for outputting the VCO output signal.
Abstract: A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V control . Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V control . Accordingly, the magnitude of total control current is dominated by the transistor-provided component, and assumes a square relationship, with respect to the input control voltage. This square-law current-voltage gain characteristic compensates for the inversely mirrored frequency gain characteristic of the ring oscillator in order to attain a reduced frequency gain variation for the overall VCO, with respect to control voltage variations. This reduction in variation translates to a reduced variation in the frequency gain of the VCO with respect to temperature variations when the VCO is used in a phase locked loop (PLL) circuit.