Showing papers on "Field-effect transistor published in 1999"

Organic-inorganic hybrid materials as semiconducting channels in thin-film field-effect transistors

Abstract: Organic-inorganic hybrid materials promise both the superior carrier mobility of inorganic semiconductors and the processability of organic materials A thin-film field-effect transistor having an organic-inorganic hybrid material as the semiconducting channel was demonstrated Hybrids based on the perovskite structure crystallize from solution to form oriented molecular-scale composites of alternating organic and inorganic sheets Spin-coated thin films of the semiconducting perovskite (C(6)H(5)C(2)H(4)NH(3))(2)SnI(4) form the conducting channel, with field-effect mobilities of 06 square centimeters per volt-second and current modulation greater than 10(4) Molecular engineering of the organic and inorganic components of the hybrids is expected to further improve device performance for low-cost thin-film transistors

Gan : processing, defects, and devices

Abstract: The role of extended and point defects, and key impurities such as C, O, and H, on the electrical and optical properties of GaN is reviewed. Recent progress in the development of high reliability contacts, thermal processing, dry and wet etching techniques, implantation doping and isolation, and gate insulator technology is detailed. Finally, the performance of GaN-based electronic and photonic devices such as field effect transistors, UV detectors, laser diodes, and light-emitting diodes is covered, along with the influence of process-induced or grown-in defects and impurities on the device physics.

Dual-material gate (DMG) field effect transistor

Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.

Ion-sensitive field-effect transistors fabricated in a commercial cmos technology

Abstract: The fabrication of pH-sensitive ISFET devices in an unmodified two-metal commercial CMOS technology (1.0 m from Atmel-ES2) is reported. The ISFET devices have a gate structure compatible with the CMOS process, with an electrically floating electrode consisting on polysilicon plus the two metals. The passivation oxynitride layer acts as the pH-sensitive material in contact with the liquid solution. The devices have shown good operating characteristics, with a 47 mV/pH response. The use of a commercial CMOS process allows the straightforward integration of signal-processing circuitry. An ISFET amplifier circuit has been integrated with the ISFET sensors.

Class AB H-bridge using current sensing MOSFETs

Abstract: An apparatus and method for supplying bi-directional load current to a load device. Four current sensing metal oxide semiconductor field effect transistors are operably configured to form an H-bridge with the load device, each transistor having separately insulated gate, source and drain and sense terminals with a source to drain conductivity determined in relation to a voltage applied to the gate terminal and a sense current from the sense terminal determined in relation to a magnitude of source to drain current. Drive voltages are applied to the gate terminals of alternating pairs of the transistors to apply the load current to the load device. The sense currents are used to provide adaptive, closed-loop clamping of the drive voltages at levels sufficient to maintain the non-load current conducting transistors in a quiescent state.

A novel ultrathin elevated channel low-temperature poly-Si TFT

Abstract: A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 /spl Aring/) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V/sub ds/=30 V, V/sub gs/=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFT's.

Titanium dioxide (TiO 2 )-based gate insulators

Abstract: Titanium dioxide has been deposited on silicon for use as a high-permittivity gate insulator in an effort to produce low-leakage films with oxide equivalent thicknesses below 2.0 nm. Excellent electrical characteristics can be achieved, but TEM and electrical measurements have shown the presence of a low-resistivity interfacial layer that we take to be SiO2. The leakage current follows several mechanisms depending on the bias voltage. Reasonably good agreement has been seen between current-voltage measurements and a 1D quantum transport model.

Gate voltage dependent mobility of oligothiophene field-effect transistors

Abstract: Organic field-effect transistors, in which the active semiconductor is made of oligothiophenes of various lengths, have been fabricated and characterized. A method is developed to estimate the field-effect mobility μ corrected for the contact series resistance. The mobility is found to increase by a factor of nearly 100 from quaterthiophene (4T) to octithiophene (8T). More importantly, μ increases quasilinearly with gate voltage. The origin of this gate bias dependence is discussed. One explanation could be the presence of traps that limit charge transport. Alternatively, the gate-voltage dependence is tentatively attributed to a dependence of the mobility with the concentration of carriers in the accumulation layer.

Insulator investigation on SiC for improved reliability

Abstract: Significant improved high-temperature reliability of SiC metal-insulator-semiconductor (MIS) devices has been achieved with both thermally grown oxides and by using a stacked dielectric consisting of silicon oxide-nitride-oxide (ONO). Capacitors of p-type 6H-SiC, n-type 6H-SiC and n-type 4H-SiC were fabricated with a variety of insulators. The best performance was accomplished only with insulators incorporating silicon dioxide. A new thermal oxidation process of growing a dry oxide then following with a wet re-oxidation anneal produces an oxide with the dielectric strength of a dry oxide and the high-quality interface of a wet oxide. MIS field effect transistors (MISFETs) with an ONO gate insulator had surface channel mobilities similar to MISFETs with thermal gate oxides, and demonstrated a lifetime of 10 days at 335/spl deg/C and 15 V bias. The lifetime of the ONO MISFET was a factor of 100 higher than for devices fabricated with deposited oxides, which had been the prior state of the art for high-temperature MISFETs on SiC.

Electronic displays using organic-based field effect transistors

Abstract: A display comprises an encapsulated display media addressed by an organic-based field effect transistor. The display media comprises a plurality of particles and a fluid. The field effect transistor comprises an organic semiconductor.

Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering

Abstract: A method of modifying the mobility of a transistor. First, a transistor having a gate is formed. A substance is then implanted in the gate. The transistor is annealed such that the implanted substance forms at least one void in the transistor's gate.

Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response

Abstract: A low drop-out (LDO) voltage regulator ( 10 ) and system ( 100 ) including the same are disclosed. An error amplifier ( 38 ) controls the gate voltage of a source follower transistor ( 24 ) in response to the difference between a feedback voltage (V FB ) from the output (V OUT ) and a reference voltage (V REF ). The source of the source follower transistor ( 24 ) is connected to the gates of an output transistor ( 12 ), which drives the output (V OUT ) from the input voltage (V IN ) in response to the source follower transistor ( 24 ). A current mirror transistor ( 14 ) has its gate also connected to the gate of the output transistor ( 12 ), and mirrors the output current at a much reduced ratio. The mirror current is conducted through network of transistors ( 18, 22 ), and controls the conduction of a first feedback transistor ( 28 ) and a second feedback transistor ( 35 ) which are each connected to the source of the source follower transistor ( 24 ) and in parallel with a weak current source ( 34 ). The response of the first feedback transistor ( 28 ) is slowed by a resistor ( 32 ) and capacitor ( 30 ), while the second feedback transistor ( 35 ) is not delayed. As such, the second feedback transistor ( 35 ) assists transient response, particularly in discharging the gate capacitance of the output transistor ( 12 ), while the first feedback transistor ( 28 ) partially cancels load regulation effects.

Method for fabricating singe crystal materials over CMOS devices

Abstract: An aspect of the present invention is a method for making a functional active device (photodetector, laser, LED, optical modulator, optical switch, field effect transistor, MOSFET, MODFET, high electron mobility transistor, heterojunction bipolar transistor, resonant tunneling device, Esaki tunneling device etc.) disposed over a complementary metal oxide semiconductor (CMOS) device, having the steps; (a) forming an ultrathin compliant layer direct bonded to an oxide layer over said-CMOS device; (b) growing an epitaxial layer on said ultra-thin compliant layer (c) forming a functional active device in said epitaxial layer grown on said epitaxial layer that is grown on said ultrathin compliant layer; and (c) interconnecting said functional active device and said CMOS device, wherein said CMOS device is configured as either a readout circuit or a control circuit for said photodetector.

Manufacture of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method with a few of masking steps. SOLUTION: N films 54, 56 and silicon oxide film 50 beneath the N films 54, 56 are masked, a polysilicon layer 48 is implanted with high concn. P ions at a low implanting energy and with low concn. P ions at a high implanting energy. Accordingly, a gate electrode 66 of a MOS field effect transistor T is implanted with the high concn. P ions and low concn. P ions, and a high resistance conductor part 64 of a high resistance element R and lower electrode 62 of a capacitor C are implanted with the low concn. P ions only. The N film 54 and an O film 58 (silicon oxide film 50) used as a mask for implanting P ions are utilized for forming a dielectric film of the capacitor C. Thus the masking step for forming a part of a dielectric film of the capacitor C contacting the lower electrode 62 can be omitted.

Spin-valve effects in a semiconductor field-effect transistor: A spintronic device

Abstract: We present a spintronic semiconductor field-effect transistor. The injector and collector contacts of this device were made from magnetic permalloy thin films with different coercive fields so that they could be magnetized either parallel or antiparallel to each other in different applied magnetic fields. The conducting medium was a two-dimensional electron gas (2DEG) formed in an AlSb/InAs quantum well. Data from this device suggest that its resistance is controlled by two different types of spin-valve effect: the first occurring at the ferromagnet-2DEG interfaces; and the second occurring in direct propagation between contacts.

Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m MOSFET's with epitaxial and /spl delta/-doped channels

Abstract: A detailed three-dimensional (3-D) statistical "atomistic" simulation study of fluctuation-resistant sub 0.1-/spl mu/m MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-/spl mu/m generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channels. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-/spl mu/m MOSFET's.

Sub-40 nm ptsi schottky source/drain metal-oxide-semiconductor field-effect transistors

Abstract: PtSi source/drain p-type metal–oxide–semiconductor field-effect transistors (MOSFETs) have been fabricated at sub-40 nm channel lengths with 19 A gate oxide. These devices employ gate-induced field emission through the PtSi ∼0.2 eV hole barrier to achieve current drives of ∼350 μA/μm at 1.2 V supply. Delay times estimated by the CV/I metric extend scaling trends of conventional p-MOSFETs to ∼2 ps. Thermal emission limits on/off current ratios to ∼20–50 in undoped devices at 300 K, while ratios of ∼107 are measured at 77 K. Off-state leakage can be reduced by implanting a thin layer of fully depleted donors beneath the active region to augment the Schottky barrier height or by use of ultrathin silicon-on-insulator substrates.

Electrical transport measurements on single-walled carbon nanotubes

Abstract: We review transport measurements on single-walled carbon nanotubes contacted by metal electrodes. At room temperature some devices show transistor action similar to that of p-channel field effect transistors, while others behave as gate-voltage independent wires. At low temperatures transport is usually dominated by Coulomb blockade. In this regime the quantum eigenstates of the finite-length tubes can be studied. At higher temperatures power law behaviour is observed for the temperature and bias dependence of the conductance. This is consistent with tunneling into a one-dimensional Luttinger liquid in a nanotube. We also discuss recent developments in contacting nanotubes which should soon allow study of their intrinsic transport properties.

Methods for designing standard cell transistor structures

Abstract: Disclosed are methods for designing standard cell transistor layouts for minimizing transistor delays and for minimizing power consumption. The method of minimizing transistor delays includes defining a transistor model for a P-type transistor and an N-type transistor of a CMOS standard cell. The method then includes minimizing a ratio between the P-type transistor and the N-type transistor. The ratio is defined by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The optimizing is performed by substantially minimizing an average delay for the transistor structure. In this embodiment, the CMOS standard cell will define a transistor structure that is implemented to make a logic circuit. The CMOS standard cell is one of a library of standard cells, where each standard cell defines a particular logic circuit.

Thin-film transistor circuitry with reduced sensitivity to variance in transistor threshold voltage

Abstract: A circuit design technique polysilicon thin-film transistor (TFT) circuitry produces circuits that are relatively less sensitive to threshold variations among the TFT's than circuits designed using conventional techniques. The circuit is designed such that thin-film transistors that are sensitive to threshold variations are made larger than other thin-film transistors in the circuitry to minimize threshold variations among similar transistors implemented in the circuit. In one embodiment, a pixel structure for an active matrix display device implemented in polysilicon includes two transistors, a select transistor and a drive transistor. The drive transistor in the pixel structure is a thin film metal oxide silicon (MOS) transistor that includes a gate to source capacitance sufficient to hold an electrical potential which keeps the transistor in a conducting state for an image field interval. One embodiment of the pixel structure includes only the select transistor and the drive transistor. The pixel storage capacitance is entirely realized by the gate to source capacitance of the drive transistor. Another embodiment of the pixel structure includes a capacitor which is much smaller than the capacitor of a conventional active matrix pixel structure. This capacitor holds the pixel in a non-illuminated state when the drive transistor is turned off. This pixel structure may be used with any display technology that uses an active matrix and stores image data on a capacitance in the pixel, including without limitation, organic light emitting diodes, electroluminescent devices, and inorganic light emitting diodes.

Field-effect transistors based on short organic molecules

Abstract: The performance of organic based field-effect transistors (FETs) has recently known significant improvements. The mobility of organic FETs now approaches 1 cm 2 V –1 s –1 with short molecules, and 0.1 cm 2 V –1 s –1 with polymers. Here, we review recent results on these devices. Attention is paid to the models developed to account for charge transport in organic semiconductors, which present significant differences from their inorganic counterparts. In particular, the mobility is gate bias dependent, which actually mirrors a dependence of the mobility on charge concentration. This has been explained in terms of trap limited transport. The temperature dependence of the mobility is usually thermally activated, which is also consistent with trap limited transport, but could also be explained by a mechanism of small polaron hopping. Furthermore, recent measurements show that the mobility can become temperature independent, which could open the way to further improvements of the performance of organic transistors.

Transistor circuit, display panel and electronic apparatus

Abstract: A transistor circuit is provided including a driving transistor where conductance between the source and the drain is controlled in response to a supplied voltage, and a compensating transistor where the gate is connected to one of the source and the drain, the compensating transistor being connected so as to supply input signals to the gate of the driving transistor through the source and drain. In a transistor circuit where conductance control in a driving transistor is carried out in response to the voltage of input signals, it is possible to control the conductance by using input signals of a relatively low voltage and a variance in threshold characteristics of driving transistors is compensated. With this transistor circuit, a display panel that can display picture images with reduced uneven brightness is achieved.

Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein

Abstract: Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped silicon carbide charge coupling region of second conductivity type (e.g., an in-situ doped epitaxial P-type region) is also provided in the trench. This charge coupling region forms a P-N rectifying junction with the drift region that extends along a sidewall of the trench. The drift region and charge coupling region are both uniformly doped at equivalent and relatively high net majority carrier doping concentrations (e.g., 1×10 17 cm −3 ) so that both the drift region and charge coupling region can be depleted substantially uniformly when blocking reverse voltages. This combination of preferred drift and charge coupling regions improves the electric field profile in the drift region to such an extent that very low forward on-state drift region resistance can be achieved simultaneously with very high reverse blocking voltage capability. Silicon carbide switching devices that can advantageously use the preferred combination of drift and charge coupling regions include Schottky barrier rectifiers (SBRs), junction field effect transistors (JFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs).

Polarization effects in nitride semiconductor device structures and performance of modulation doped field effect transistors

Abstract: Wide bandgap nitride semiconductors have recently attracted a great level of attention owing to their direct bandgaps in the visible to ultraviolet regions of the spectrum as emitters and detectors. Moreover, this material system with its favorable hetero-junctions and transport properties began to produce very respectable power levels in microwave amplifiers. If and when the breakdown fields achieved experimentally approach the predicted values, this material system would also be very attractive for power switching devices. In addition to the premature breakdown, and high concentration of defects and inhomogeneities, a number of scientific challenges remain including a clear experimental investigation of polarization effects. In this paper, following a succinct review of the progress that has been made, spontaneous and piezoelectric polarization effects and their impact on sample device-like hetero-structures will be treated.

Electrical recordings from rat cardiac muscle cells using field-effect transistors.

Abstract: Extracellular electrophysiological recordings were made from cardiac cells cultured for up to seven days over microfabricated arrays of field-effect transistors. The recorded signals can be separated mainly into two types of cell transistor couplings: one that can be explained entirely by purely passive circuitry elements, and a second where voltage-gated ion channels contribute greatly to the measured extracellular signal.

Elevated channel mosfet

Abstract: The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized process order. The process flow of the present invention provides for the implantation and thermal processing of the wells and junctions prior to the growth of a channel or the deposition of the gate stack. By implanting and annealing the wells and junctions prior to the formation of the channel and gate, the present invention allows a greater variety of materials to be utilized as the channel and gate materials than are available under process flows currently known; undoped materials may be used to form the channel, metal oxides and similar materials with large dielectrics may be used to form a gate stack, and barrier metals and pure metals (copper, tungsten, etc.) may be used as gate electrodes. The present invention also provides for the selective epitaxial growth of a channel material elevated above the surface of a wafer containing a well and junctions. By providing an elevated channel, higher mobility may be achieved; thereby enabling a higher current flow at a lower voltage through a semiconductor device.

Work function tuning for MOSFET gate electrodes

Abstract: Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Planarized silicon fin device

Abstract: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.