Showing papers on "Field-effect transistor published in 2001"

Logic gates and computation from assembled nanowire building blocks.

Abstract: Miniaturization in electronics through improvements in established “top-down” fabrication techniques is approaching the point where fundamental issues are expected to limit the dramatic increases in computing seen over the past several decades Here we report a “bottom-up” approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale field-effect transistor arrays with nanowires as both the conducting channel and gate electrode Nanowire junction arrays have been configured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation

Carbon Nanotube Inter- and Intramolecular Logic Gates

Abstract: Single wall carbon nanotubes (SWCNTs) have been used as the active channels of field effect transistors (FET). The next development step involves the integration of CNTFETs to form logic gates; the basic units of computers. For this we need to have both p- and n-type CNTFETs. However, without special treatment, the obtained CNTFETs are always p-type: the current carriers are holes and the devices are ON for negative gate bias. Here we show that n-type CNTFETs can be prepared not only by doping but also by a simple annealing of SWNT-based p-FETs in a vacuum. We use our ability to prepare both p- and n-type nanotube transistors to build the first nanotube-based logic gates: voltage inverters. Using spatially resolved doping we implemented this logic function on a single nanotube bundle.

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Abstract: The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Limits on Silicon Nanoelectronics for Terascale Integration

Abstract: Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

High-performance bottom electrode organic thin-film transistors

Abstract: Pentacene-based organic field effect transistors (FETs) exhibit enormous potential as active elements in a number of applications. One significant obstacle to commercial application remains: no completely lithographic process exists for forming high-performance devices. Processing constraints prevent electrodes from being lithographically patterned once the semiconductor is deposited, but depositing the electrodes before the semiconductor leads to low-performance transistors. By using self-assembled monolayers (SAMs) to change the surface energy of the metal electrodes and morphology of the pentacene subsequently grown on the electrodes, high-performance transistors may be formed using a process compatible with lithographic definition of the source and drain electrodes.

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

Abstract: We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

Method of forming a double gate transistor having an epitaxial silicon/germanium channel region

Abstract: A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Current-reuse bleeding mixer

Abstract: A current-reusing bleeding mixer capable of providing a higher conversion gain, linearity and lower noise figure employing a field-effect transistor includes a first to a fourth transistor and a first and a second load element. The first transistor amplifies a radio frequency (RF) signal. The second and the third transistor, each connected to the first transistor, receive a balanced local oscillator (LO) signal to mix it with the RF signal. The first and the second load element are connected between a supply voltage source and the second transistor and between the supply voltage source and the third transistor, respectively. The fourth transistor, connected between the supply voltage source and the first transistor, amplifies the RF signal and bleeds a current from the supply voltage source.

Semiconductor device having MIS field effect transistors or three-dimensional structure

Abstract: A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed above at least the side surfaces of the semiconductor projection. Source and drain regions are formed in the side surfaces of the semiconductor projection on opposite sides of the gate electrode. First and second device isolation insulating films are formed on the semiconductor substrate on opposite sides of the semiconductor projection. A first impurity region is formed in the semiconductor substrate below the first device isolation insulating film. A second impurity region is formed in the semiconductor substrate below the second device isolation insulating film. The first and second impurity regions are in contact with each other in the semiconductor substrate below the semiconductor projection.

Electrochemical carbon nanotube field-effect transistor

Abstract: We explore the electric-field effect of carbon nanotubes (NTs) in electrolytes. Due to the large gate capacitance, Fermi energy (EF) shifts of order ±1 V can be induced, enabling to tune NTs from p to n-type. Consequently, large resistance changes are measured. At zero gate voltage, the NTs are hole-doped in air with |EF|≈0.3–0.5 eV, corresponding to a doping level of ≈1013 cm−2. Hole-doping increases in the electrolyte.

Si 3 N 4 /AlGaN/GaN-Metal-Insulator-Semiconductor Heterostructure Field-Effect Transistors

Abstract: We report on a metal–insulator–semiconductor heterostructure field-effect transistor (MISHFET) using Si3N4 film simultaneously for channel passivation and as a gate insulator. This design results in increased radio-frequency (rf) powers by reduction of the current collapse and it reduces the gate leakage currents by four orders of magnitude. A MISHFET room temperature gate current of about 90 pA/mm increases to only 1000 pA/mm at ambient temperature as high as 300 °C. Pulsed measurements show that unlike metal–oxide–semiconductor HFETs and regular HFETs, in a Si3N4 MISHFET, the gate voltage amplitude required for current collapse is much higher than the threshold voltage. Therefore, it exhibits significantly reduced rf current collapse.

High speed composite p-channel Si/SiGe heterostructure for field effect devices

Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

Group iii nitride based fets and hemts with reduced trapping and method for producing the same

Abstract: New Group III nitride based field effect transistors (10) and high electron mobility transistors (30) are disclosed that provide enhanced high frequency response characteristics. The preferred transistors (10, 30) are made from GaN/AlGaN and have a dielectric layer (22, 44) on the surface of their barrier layer (18, 38). The dielectric layer (22, 44) has a high percentage of donor electrons (68) that neutralize traps (69) in the barrier layer (18, 38) such that the traps (69) cannot slow the high frequency response of the transistors (10, 30). A new method of manufacturing the transistors (10, 30) is also disclosed, with the new method using sputtering to deposit the dielectric layer (18, 38).

Bias stress in organic thin-film transistors and logic gates

Abstract: Threshold voltage instabilities of all-organic thin-film transistors are investigated as a function of stress time and stress bias. The dominant effect is a positive threshold shift for negative gate bias stress which is explained by mobile ions drifting in the insulator when a gate field is applied. Trapping of charge carriers at the semiconductor–insulator interface plays only a minor role. Furthermore, we investigate the stress behavior of a basic logic element, an inverter. In comparison to a single transistor, we observe improved stability which arises from partial compensation of the parametric shifts during operation.

Light responsive polymer field-effect transistor

Abstract: We report the effect of light incident on a polymer-based field-effect transistor and demonstrate the utility of light as an additional controlling parameter of the transistor state. The transistor exhibits large photosensitivity indicated by the sizable changes in the drain–source current at low levels of light. The response here is considerably higher than that from existing organic/polymeric planar, two-terminal photodetectors due to an additional process contributing to the enhancement. The light-responsive polymer transistor opens up a device-architecture concept for polymer-based electronics.

Gallium nitride based high power heterojunction field effect transistors: process development and present status at UCSB

Abstract: The development of GaN based devices for microwave power electronics at the University of California, Santa Barbara (UCSB), is reviewed. From 1995 to 2000, the power performance of AlGaN/GaN-on-sapphire heterojunction field effect transistors improved from 1.1 W/mm to 6.6 W/mm, respectively. Compensating the disadvantages of the low thermal conductivity of the sapphire substrate through heat management via flip chip bonding onto AlN substrates, large periphery devices with an output power of 7.6 W were demonstrated. UCSB also fabricated the first GaN based amplifier integrated circuits. Critical issues involved in the growth of high quality AlGaN/GaN heterostructures by metal-organic chemical vapor deposition and the device fabrication are discussed.

Self-assembled monolayer organic field-effect transistors

Abstract: The use of individual molecules as functional electronic devices was proposed in 1974 (ref. 1). Since then, advances in the field of nanotechnology have led to the fabrication of various molecule devices and devices based on monolayer arrays of molecules2,3,4,5,6,7,8,9,10,11. Single molecule devices are expected to have interesting electronic properties, but devices based on an array of molecules are easier to fabricate and could potentially be more reliable. However, most of the previous work on array-based devices focused on two-terminal structures: demonstrating, for example, negative differential resistance8, rectifiers9, and re-configurable switching10,11. It has also been proposed that diode switches containing only a few two-terminal molecules could be used to implement simple molecular electronic computer logic circuits12. However, three-terminal devices, that is, transistors, could offer several advantages for logic operations compared to two-terminal switches, the most important of which is ‘gain’—the ability to modulate the conductance. Here, we demonstrate gain for electronic transport perpendicular to a single molecular layer (∼10–20 A) by using a third gate electrode. Our experiments with field-effect transistors based on self-assembled monolayers demonstrate conductance modulation of more than five orders of magnitude. In addition, inverter circuits have been prepared that show a gain as high as six. The fabrication of monolayer transistors and inverters might represent an important step towards molecular-scale electronics.

Design and fabrication of organic complementary circuits

Abstract: We have used a simple model description of single field effect transistor characteristics to design organic complementary circuits ranging in complexity from simple inverters through 48-stage shift registers and three-bit row decoders. The circuits were fabricated using standard silicon photolithographic techniques to define the metal, insulator, and interconnect levels. The ohmic source and drain contacts and part of the interconnect metallization were formed by electroless/immersion deposition of Ni-P/Au on prepatterned TiN. The n-type and p-type organic semicondcutors were evaporated onto these substrates to complete the circuits. Measured circuit characteristics were in reasonable agreement with simulations based on the simple device model.

Method for improving performance of organic semiconductors in bottom electrode structure

Abstract: A method for improving the performance of an organic thin film field effect transistor comprising the steps of: (a) forming a transistor structure having patterned source and drain electrodes; and (b) treating the patterned source and drain electrodes with a thiol compound having the formula, RSH, wherein R is a linear or branched, substituted or unsubstituted, alkyl, alkenyl, cycloalkyl or aromatic containing from about 6 to about 25 carbon atoms under conditions that are effective in forming a self-assembled monolayer of said thiol compound on said electrodes. Organic thin film transistor structures containing the self-assembled monolayer of the present invention are also disclosed.

Fin field effect transistor with self-aligned gate

Abstract: The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

Influence of impact-ionization-induced instabilities on the maximum usable output voltage of Si-bipolar transistors

Abstract: The onset of impact-ionization-induced instabilities limits the operating range of Si-bipolar transistors, especially in power stages. Therefore, analytical relations which characterize the onset of instabilities are derived for different driving conditions (mainly V/sub BE/=const. and I/sub E/=const.) and arbitrary transistor geometries. They allow the designer and technologist to calculate the maximum usable dc output voltage in dependence on transistor dimensions and technological parameters. As a consequence, the voltage range above BV/sub CE0/ can now be more intensively and reliably used and thus the performance potential of a given technology can be better exploited. However, the reduction of the maximum tolerable output voltage with increasing emitter (or collector) current must be carefully considered. The presented theory and analytical results are verified by three-dimensional (3-D) transistor simulations and by measurements.

Methodology for control of short channel effects in MOS transistors

Abstract: A method of improving short channel effects in a transistor. First, a substance is implanted in a substrate. The substrate is then annealed such that the implanted substance forms at least one void in the substrate. Then, a transistor having a source, a drain, and a channel region is formed on the substrate, wherein the at least one void is in the channel region of the transistor.

Field-effect transistor based on embedded cluster structures and process for its production

Abstract: Field-Effect Transistor Based on Embedded Cluster Structures and Process for Its Production In field-effect transistors, semiconductor clusters, which can extend from the source region to the drain region and which can be implemented in two ways, are embedded in one or a plurality of layers. In a first embodiment, the semiconductor material of the adjacent channel region can be strained by the clusters and the effective mass can thus be reduced by altering the energy band structure and the charge carrier mobility can be increased. In a second embodiment, the clusters themselves can be used as a canal region. These two embodiments can also appear in mixed forms. The invention can be applied to the Si material system with SiGe clusters or to the GaAs material system with InGaAs clusters or to other material systems.

Low-power organic light emitting diode pixel circuit

Abstract: A pixel circuit comprises an organic light emitting diode (OLED), and a static memory for storing data that represents an operational state of the OLED. In alternative embodiments, a pixel circuit may include a complementary metal oxide semiconductor (CMOS) circuit for controlling the OLED, a protection circuit for protecting the CMOS circuit from an over-voltage condition, and a current source with a field effect transistor (FET) having a static gate to source voltage that is greater than a threshold voltage of the FET.

Ultraclean two-stage aerosol reactor for production of oxide-passivated silicon nanoparticles for novel memory devices

Abstract: Silicon nanoparticle-based floating gate metal oxide semiconductor field effect devices are attractive candidates for terabit cm^–2 density nonvolatile memory applications. We have designed an ultraclean two-stage aerosol process reactor and 200 mm wafer deposition chamber in order to integrate Si/SiO2 nanoparticles into memory devices. In the first stage, silicon nanoparticles are synthesized by thermal decomposition of silane gas in a reactor that has been optimized to produce nonagglomerated nanoparticles at rates sufficient for layer deposition. In the second stage, the silicon particles are passivated with thermal oxide that partly consumes the particle. This two-stage aerosol reactor has been integrated to a 200 mm silicon wafer deposition chamber that is contained within a class 100 cleanroom environment. This entire reactor system conforms to rigorous cleanliness specifications such that we can control transition metal contamination to as good as 10^10 atoms cm^–2. The deposition chamber has been designed to produce a controllable particle density profile along a 200 mm wafer where particles are thermophoretically deposited uniformly over three-quarters of the wafer. Thus, we now have the capability to deposit controlled densities of oxide-passivated silicon nanoparticles onto 200 mm silicon wafers for production of silicon nanoparticle memory devices.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

Abstract: We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Potentiometry of an operating organic semiconductor field-effect transistor

Abstract: The potential profile across the channel of an operating sexithiophene-based field-effect transistor (FET) was investigated using an atomic force microscope with a conducting probe. A high impedance electrometer recorded the probe potential when it was placed in contact at fixed points with the channel surface. Tapping mode images taken with the same probe before and after individual point contact measurements verified that no damage was done to the device and allowed correlation of the potential profile with the device architecture. For any given source-drain bias, most of the potential drop occurred at the source and drain contacts, meaning the FET was contact limited. Moreover, the potential drop was not fixed but depended on the applied drain and gate voltages. This study demonstrates the utility of potential profiling for identifying high resistance bottlenecks to charge transport in organic-based devices.

Electrolyte-Solution-Gate FETs Using Diamond Surface for Biocompatible Ion Sensors

Abstract: Diamond field effect transistors have operated in electrolyte solution for the first time Since the hydrogen-terminated diamond surfaces are stable enough for the use as an electrochemical electrode, the diamond surface channels are exposed to the electrolyte in the transistor structure A perfect pinch-off and saturated current-voltage characteristics have been obtained for bias voltages within the potential window The threshold voltages are almost constant in electrolytes with different pH values of 7-13, indicating pH insensitiveness of the hydrogen-terminated diamond surface Based on this pH insensitive surface, ion selective regions can be fabricated to form transistor-based biosensors

Self-assembled Ge/Si dots for faster field-effect transistors

Abstract: Self-assembled and coherently strained germanium nanostructured dots are grown on prepatterned Si substrates along ordered lines. These precisely aligned nanocrystals are proposed to make up the central unit of a dot-based field-effect transistor (DotFET). The strain-induced band edge splitting and the inherently smaller effective masses of charge carriers in Ge/Si dots promise faster transistors than are possible for conventional pure Si devices. Thick relaxed buffer layers-mandatory for any existing high-speed SiGe field-effect devices-are no longer required. The DotFET is straight-forward, defect-free, and fully compatible with current complementary metal-oxide-semiconductor (CMOS) technology.

AlGaN/InGaN/GaN Double Heterostructure Field-Effect Transistor

Abstract: Novel, current collapse free, double heterostructure AlGaN/InGaN/GaN field effect transistors (DHFETs) are fabricated on the insulating SiC substrates. The simulations show that a combined effect of the bandgap offsets and polarization charges provides an excellent 2D carrier confinement. These devices demonstrate output RF powers as high as 4.3 W/mm in CW mode and 6.3 W/mm in the pulsed mode, with the gain compression as low as 4 dB.