Showing papers on "Field-effect transistor published in 2002"

Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes

Abstract: We have fabricated single-wall carbon nanotube field-effect transistors (CNFETs) in a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric These top gate devices exhibit excellent electrical characteristics, including steep subthreshold slope and high transconductance, at gate voltages close to 1 V—a significant improvement relative to previously reported CNFETs which used the substrate as a gate and a thicker gate dielectric Our measured device performance also compares very well to state-of-the-art silicon devices These results are observed for both p- and n-type devices, and they suggest that CNFETs may be competitive with Si MOSFETs for future nanoelectronic applications

Controlling doping and carrier injection in carbon nanotube transistors

Abstract: Carbon nanotube field-effect transistors (CNTFETs) fabricated out of as-grown nanotubes are unipolar p-type devices. Two methods for their conversion from p- to n-type devices are presented. The first method involves conventional doping with an electron donor, while the second consists of annealing the contacts in vacuum to remove adsorbed oxygen. A comparison of these methods shows fundamental differences in the mechanism of the transformation. The key finding is that the main effect of oxygen adsorption is not to dope the bulk of the tube, but to modify the barriers at the metal–semiconductor contacts. The oxygen concentration and the level of doping of the nanotube are therefore complementary in controlling the CNTFET characteristics. Finally, a method of controlling individually the contact barriers by local heating is demonstrated.

FinFET scaling to 10 nm gate length

Abstract: While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm These MOSFETs are believed to be the smallest double-gate transistors ever fabricated Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm) The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 12 V Working CMOS FinFET inverters are also demonstrated

Nanoscale wires and related devices

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

Trapping effects in GaN and SiC microwave FETs

Abstract: It is well known that trapping effects can limit the output power performance of microwave field-effect transistors (FETs). This is particularly true for the wide bandgap devices. In this paper we review the various trapping phenomena observed in SiC- and GaN-based FETs that contribute to compromised power performance. For both of these material systems, trapping effects associated with both the surface and with the layers underlying the active channel have been identified. The measurement techniques utilized to identify these traps and some of the steps taken to minimize their effects, such as modified buffer layer designs and surface passivation, are described. Since similar defect-related phenomena were addressed during the development of the GaAs technology, relevant GaAs work is briefly summarized.

Two-dimensional quantum mechanical modeling of nanotransistors

Abstract: Quantization in the inversion layer and phase coherent transport are anticipated to have significant impact on device performance in “ballistic” nanoscale transistors. While the role of some quantum effects have been analyzed qualitatively using simple one-dimensional ballistic models, two-dimensional (2D) quantum mechanical simulation is important for quantitative results. In this paper, we present a framework for 2D quantum mechanical simulation of a nanotransistor/metal oxide field effect transistor. This framework consists of the nonequilibrium Green’s function equations solved self-consistently with Poisson’s equation. Solution of this set of equations is computationally intensive. An efficient algorithm to calculate the quantum mechanical 2D electron density has been developed. The method presented is comprehensive in that treatment includes the three open boundary conditions, where the narrow channel region opens into physically broad source, drain and gate regions. Results are presented for (i) dr...

Why is nonvolatile ferroelectric memory field-effect transistor still elusive?

Abstract: In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.

Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators

Abstract: This work demonstrates multistage complementary NOR, OR, NAND, and AND logic gates and ring oscillators (frequency ∼220 Hz) with arrays of p- and n-type nanotube field effect transistors (FETs). The demonstration is made possible by progress in three aspects of nanotube synthesis and integration. First, patterned growth leads to large numbers of nanotube FETs in an array, as up to 70% of individual nanotubes are semiconductors. Second, metal electrodes are successfully embedded underneath nanotubes and used as local gates. Third, complementary logic gates are made possible by converting p-type FETs in an array into n-type FETs by a local electrical manipulation and doping approach.

Nonresonant Detection of Terahertz Radiation in Field Effect Transistors

Abstract: We present an experimental and theoretical study of nonresonant detection of subterahertz radiation in GaAs/AlGaAs and GaN/AlGaN heterostructure field effect transistors. The experiments were performed in a wide range of temperatures (8–300 K) and for frequencies ranging from 100 to 600 GHz. The photoresponse measured as a function of the gate voltage exhibited a maximum near the threshold voltage. The results were interpreted using a theoretical model that shows that the maximum in photoresponse can be explained by the combined effect of exponential decrease of the electron density and the gate leakage current.

Radiation Effects in Advanced Semiconductor Materials and Devices

Abstract: Radiation Environments and Component Selection Strategy.- Basic Radiation Damage Mechanisms in Semiconductor Materials and Devices.- Displacement Damage in Group IV Semiconductor Materials.- Radiation Damage in GaAs.- Space Radiation Aspects of Silicon Bipolar Technologies.- Radiation Damage in Silicon MOS Devices.- GaAs Based Field Effect Transistors for Radiation-Hard Applications.- Opto-Electronic Components for Space.- Advanced Semiconductor Materials and Devices - Outlook.

Carbon nanotube electronics

Abstract: Presents experimental results on single-wall carbon nanotube field-effect transistors (CNFETs) operating at gate and drain voltages below 1V. Taking into account the extremely small diameter of the semiconducting tubes used as active components, electrical characteristics are comparable with state-of-the-art metal oxide semiconductor field-effect transistors (MOSFETs). While output as well as subthreshold characteristics resemble those of conventional MOSFETs, we find that CNFET operation is actually controlled by Schottky barriers (SBs) in the source and drain region instead of by the nanotube itself. Due to the small size of the contact region between the electrode and the nanotube, these barriers can be extremely thin, enabling good performance of SB-CNFETs.

Non-volatile molecular memory elements based on ambipolar nanotube field effect transistors

Abstract: We have fabricated air-stable n-type, ambipolar carbon nanotube field effect transistors (CNFETs), and used them in nanoscale memory cells. N-type transistors are achieved by annealing of nanotubes in hydrogen gas and contacting them by cobalt electrodes. Scanning gate microscopy reveals that the bulk response of these devices is similar to gold-contacted p-CNFETs, confirming that Schottky barrier formation at the contact interface determines accessibility of electron and hole transport regimes. The transfer characteristics and Coulomb Blockade (CB) spectroscopy in ambipolar devices show strongly enhanced gate coupling, most likely due to reduction of defect density at the silicon/silicon-dioxide interface during hydrogen anneal. The CB data in the ``on''-state indicates that these CNFETs are nearly ballistic conductors at high electrostatic doping. Due to their nanoscale capacitance, CNFETs are extremely sensitive to presence of individual charge around the channel. We demonstrate that this property can be harnessed to construct data storage elements that operate at the few-electron level.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Noncontact potentiometry of polymer field-effect transistors

Abstract: We report on high-resolution potentiometry of operating organic thin-film field-effect transistors by means of scanning Kelvin probe force microscopy. It is demonstrated that the measured potential reflects the electrostatic potential of the accumulation layer at the semiconductor/insulator interface. We present data revealing gate bias and lateral electric field dependence of the field-effect mobility in poly(hexylthiophene) at temperatures from 50 to 300 K.

Nonvolatile Molecular Memory Elements Based on Ambipolar Nanotube Field Effect Transistors

Abstract: We have fabricated air-stable n-type, ambipolar carbon nanotube field effect transistors (CNFETs) and used them in nanoscale memory cells. n-Type transistors are achieved by annealing nanotubes in hydrogen gas and contacting them by cobalt electrodes. Scanning gate microscopy reveals that the bulk response of these devices is similar to gold-contacted p-CNFETs, confirming that Schottky barrier formation at the contact interface determines accessibility of electron and hole transport regimes. The transfer characteristics and Coulomb blockade (CB) spectroscopy in ambipolar devices show strongly enhanced gate coupling, most likely due to reduction of defect density at the silicon/silicon-dioxide interface during hydrogen anneal. The CB data in the “on”-state indicates that these CNFETs are nearly ballistic conductors at high electrostatic doping. Due to their nanoscale capacitance, CNFETs are extremely sensitive to the presence of individual charges around the channel. We demonstrate that this property can b...

Terahertz photoconductivity and plasmon modes in double-quantum-well field-effect transistors

Abstract: Double-quantum-well field-effect transistors with a grating gate exhibit a sharply resonant, voltage tuned terahertz photoconductivity The voltage tuned resonance is determined by the plasma oscillations of the composite structure The resonant photoconductivity requires a double-quantum well but the mechanism whereby plasma oscillations produce changes in device conductance is not understood The phenomenon is potentially important for fast, tunable terahertz detectors

Resonant detection of subterahertz and terahertz radiation by plasma waves in submicron field-effect transistors

Abstract: We report on the experiments on resonant photoresponse of the gated two-dimensional electron gas to the terahertz radiation. The visible-light-induced, metastable increase of the carrier density in the transistor channel shifts the resonance position to the higher gate voltages, in agreement with plasma wave detection theory. In this way, an unambiguous proof of the origin of the observed resonant detection is provided. The visible light illumination also leads to an increase of the electron mobility and, as a result, to an increase of the resonant detection quality factor. Resonant detection of the harmonics of the Gunn diode-based emission system is demonstrated up to 1.2 THz.

A spacer patterning technology for nanoscale CMOS

Abstract: A spacer patterning technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-7 nm structures with conventional dry etching. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension (CD) variations of minimum-sized features much smaller than that achieved by optical or e-beam lithography. In addition, it also provides a doubling of device density for a given lithography pitch. This method is used to pattern silicon fins for double-gate metal-oxide semiconductor field effect transistors (MOSFETs) (FinFETs) and gate electrode structures for ultrathin body MOSFETs. Process details are presented.

Carrier transport and density of state distributions in pentacene transistors

Abstract: We present a density of state model for the transport properties of pentacene field effect transistors. Using a one-dimensional transistor model we study the effect of different localized trap distributions on the current-voltage characteristics of such devices. We find that a distributed trap model with a steep exponential band tail of donors and a shallower exponential tail of acceptors inside the band gap can describe consistently our experimental data obtained from bottom-gate polycrystalline pentacene transistors for different gate dielectrics and under various external conditions.

Performance projections for ballistic carbon nanotube field-effect transistors

Abstract: The performance limits of carbon nanotube field-effect transistors (CNTFETs) are examined theoretically by extending a one-dimensional treatment used for silicon metal–oxide–semiconductor field-effect transistors (MOSFETs). Compared to ballistic MOSFETs, ballistic CNTFETs show similar I–V characteristics but the channel conductance is quantized. For low-voltage, digital applications, the CNTFET with a planar gate geometry provides an on-current that is comparable to that expected for a ballistic MOSFET. Significantly better performance, however, could be achieved with high gate capacitance structures. Because the computed performance limits greatly exceed the performance of recently reported CNTFETs, there is considerable opportunity for progress in device performance.

Driving circuit for current control element and image display device

Abstract: PROBLEM TO BE SOLVED: To eliminate the influence of variance in the threshold characteristic of a driving transistor. SOLUTION: The disclosed driving circuit for the current control element has the driving transistor 6 and current control element 7 which are connected in series between a power line 1 and a ground line 2, a hold capacitor 5 which is connected between the connection point between the driving transistor 6 and current control element 7 and the gate electrode of the driving transistor 6, and a select gate transistor 4 which is connected between a signal line 3 and the gate electrode of the driving transistor 6. Then the driving circuit turns on the select gate transistor 4 in a selection period to input a 1st signal voltage from the signal line 3, inputs and holds a 2nd signal voltage from the signal line 3 in the hold capacitor 5 after discharging signal charges written to the hold capacitor 5 through the driving transistor 6, and turns off the select gate transistor 4 in a non-selection period to supply a current to the current control element 7 through the driving transistor 6. COPYRIGHT: (C)2003,JPO

Organic field-effect transistors with polarizable gate insulators

Abstract: A quasi-stable threshold voltage (Vt) shift is imparted onto field-effect transistors (FETs) with organic semiconductors and polymer dielectrics. Adjustment of Vt from accumulation mode to zero or depletion mode is demonstrated for both p-channel and n-channel FETs, and is accomplished by applying a depletion voltage to the gate prior to device operation. Hydrophobic dielectrics and dopant-resistant semiconductors were advantageous. A pixel circuit that utilizes this nonvolatile memory element is proposed.

Thin-film transistors based on well-ordered thermally evaporated naphthacene films

Abstract: We report on organic thin-film transistors fabricated using the small-molecule organic semiconductor naphthacene as the active layer material with device performance suitable for several large-area or low-cost electronics applications. We investigated naphthacene thin films deposited by thermal evaporation onto amorphous substrates held near room temperature. Using atomic-force microscopy and x-ray diffraction we find naphthacene films consist of a high density of submicron-sized grains with a surprisingly high degree of molecular order. Thin-film transistors fabricated using evaporated naphthacene films on thermally oxidized silicon substrates have field-effect mobility larger than 0.1 cm2/V s, current on/off ratio greater than 106, negative threshold voltage, and subthreshold slope of 1 V/decade.

Resonant detection of subterahertz radiation by plasma waves in a submicron field-effect transistor

Abstract: The resonant detection of subterahertz radiation by two-dimensional electron plasma confined in a submicron gate GaAs/AlGaAs field-effect transistor is demonstrated. The results show that the critical parameter that governs the sensitivity of the resonant detection is ωτ, where ω is the radiation frequency and τ is the momentum scattering time. By lowering the temperature and hence increasing τ and increasing the detection frequency ω, we reached ωτ∼1 and observed resonant detection of 600 GHz radiation in a 0.15 μm gate length GaAs field-effect transistor. The evolution of the observed photoresponse signal with temperature and frequency is reproduced well within the framework of a theoretical model.

Nanotechnology goals and challenges for electronic applications

Abstract: Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today's 0.13-/spl mu/m generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs.

High-voltage lateral transistor with a multi-layered extended drain structure

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Electrical Interfacing of Nerve Cells and Semiconductor Chips

Abstract: The electrical interfacing of individual nerve cells and silicon microstructures is considered, as well as the assembly of elementary hybrid systems made of neuronal networks and semiconductor microelectronics. Without electrochemical processes, coupling of the electron-conducting semiconductor and the ion-conducting neurons relies on a close contact of cell membrane and oxidised silicon with a high resistance of the junction and a high conductance of the attached membrane. Neuronal excitation can be elicited and recorded from the chip by capacitive contacts and by field-effect transistors with an open gate. Integrated iono-electronic system are obtained by the outgrowth of neuronal networks on the surface of the silicon chip, by implementing electrical circuits in the chip and by two-way interfacing of the neuronal and the electronic components.

A compact scattering model for the nanoscale double-gate MOSFET

Abstract: An analytically compact model for the nanoscale double gate metal-oxide semiconductor field effect transistor (MOSFET) based on McKelvey's flux theory is developed. The model is continuous above and below threshold and from the linear to saturation regions. Most importantly, it describes nanoscale MOSFETs from the diffusive to ballistic regimes. In addition to its use in exploring the limits and circuit applications of double gate MOSFETs, the model also serves as an example of how semiclassical scattering theory can be used to develop physically sound models for nanoscale transistors.

Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Subthreshold characteristics of field effect transistors based on poly(3-dodecylthiophene) and an organic insulator

Abstract: The properties of field effect transistors with organic insulator and semiconducting regions, fabricated with a top-gate architecture, have been investigated. Thin films (d≈30 nm) of regioregular poly(3-dodecylthiophene) were employed as the active semiconductor and the gate insulator was formed by a 500-nm-thick layer of poly(4-vinylphenol). Both were solution-processed on top of poly(ethylenetherephthalate) films, which were used as substrates. The output characteristics show a pronounced saturation behavior with an unconventional nonquadratic saturation current dependence on the gate voltage. Hence the (hole) mobility of 0.002–0.005 cm2/Vs has been estimated from the linear region of the transfer characteristics. The transistor turn-on occurs at a threshold voltage of approximately Vth=0 V, and the device can be operated with a supply voltage of between 15 and 20 V. As is usually observed for organic transistors, the inverse subthreshold slope (S) is very high, in our case S≈7 V/dec, by contrast with S...