Showing papers on "Field-effect transistor published in 2008"

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

Abstract: It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.

Thin film transistor and organic light-emitting display device having the thin film transistor

Abstract: Disclosed is a thin film transistor including a P-type semiconductor layer, and an organic light-emitting display device having the thin film transistor. The present invention provides a thin film transistor including a substrate, a semiconductor layer, and a gate electrode and a source/drain electrode formed on the substrate, wherein the semiconductor layer is composed of P-type ZnO:N layers through a reaction of a mono-nitrogen gas with a zinc precursor, and the ZnO:N layer includes an un-reacted impurity element at a content of 3 at % or less.

Field-effect transistor and method for manufacturing the same

Abstract: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from the source electrode and the drain electrode to the oxide semiconductor layer.

Solution-gated epitaxial graphene as pH sensor.

Abstract: A solution-gate field effect transistor (SGFET) has been fabricated on few-layer graphene (FLG). The ideally polarizable graphene/aqueous electrolyte interface allows the capacitive charging of the surface by hydroxyl (OH-) and hydroxonium ions (H3O+). The conductivity versus gate potential curve exhibits "V" shaped ambipolar transfer characteristics of graphene, with hole and electron mobilities of 3600 cm2/Vs and 2100 cm2/Vs, respectively. The shift of the negative gate potential with pH shows a supra-Nernstian response of 99 meV/pH. Our work points to the potential application of graphene in ultrafast and ultralow noise chemical or biological sensors.

Nanowire Transistor Performance Limits and Applications

Abstract: Semiconductor nanowires represent unique materials for exploring phenomena at the nanoscale. Developments in nanowire growth have led to the demonstration of a wide range of nanowire materials with precise control of composition, morphology, and electrical properties, and it is believed that this excellent control together with small channel size could yield device performance exceeding that obtained using top-down techniques. Here, we review advances in chemically synthesized semiconductor nanowires as nanoelectronic devices. We first introduce basic nanowire field-effect transistor structures and review results obtained from both p- and n-channel homogeneous composition nanowires. Second, we describe nanowire heterostructures, show that by using nanowire heterostructures, several limiting factors in homogeneous nanowire devices can be mitigated, and demonstrate that nanowire transistor performance can reach the ballistic limit and exceed state-of-the-art planar devices. Third, we discuss basic methods for organization of nanowires necessary for fabricating arrays of device and circuits. Fourth, we introduce the concept of crossbar nanowire circuits, discuss results for both transistor and nonvolatile switch devices, and describe unique approaches for multiplexing/demultiplexing enabled by synthetically coded nanowire. Fifth, we discuss the unique application of thin-film nanowire transistor arrays on low-cost substrates and illustrate this with results for relatively high-frequency ring oscillators and completely transparent device arrays. Finally, we describe 3-D heterogeneous integration that is uniquely enabled by multifunctional nanowires within a bottom-up approach.

Bottom-up organic integrated circuits

Abstract: Self-assembly—the autonomous organization of components into patterns and structures1—is a promising technology for the mass production of organic electronics. Making integrated circuits using a bottom-up approach involving self-assembling molecules was proposed2 in the 1970s. The basic building block of such an integrated circuit is the self-assembled-monolayer field-effect transistor (SAMFET), where the semiconductor is a monolayer spontaneously formed on the gate dielectric. In the SAMFETs fabricated so far, current modulation has only been observed in submicrometre channels3–5, the lack of efficient charge transport in longer channels being due to defects and the limited intermolecular p–p coupling between the molecules in the selfassembled monolayers. Low field-effect carrier mobility, low yield and poor reproducibility have prohibited the realization of bottom-up integrated circuits. Here we demonstrate SAMFETs with long-range intermolecular p–p coupling in the monolayer. We achieve dense packing by using liquid-crystalline molecules consisting of a p-conjugated mesogenic core separated by a long aliphatic chain from a monofunctionalized anchor group. The resulting SAMFETs exhibit a bulk-like carrier mobility, large current modulation and high reproducibility. As a first step towards functional circuits, we combine the SAMFETs into logic gates as inverters; the small parameter spread then allows us to combine the inverters into ring oscillators. We demonstrate real logic functionality by constructing a 15-bit code generator in which hundreds of SAMFETs are addressed simultaneously. Bridging the gap between discrete monolayer transistors and functional selfassembled integrated circuits puts bottom-up electronics in a new perspective.

Toward Nanowire Electronics

Abstract: This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

Organic non-volatile memories from ferroelectric phase-separated blends

Abstract: New non-volatile memories are being investigated to keep up with the organic-electronics road map. Ferroelectric polarization is an attractive physical property as the mechanism for non-volatile switching, because the two polarizations can be used as two binary levels. However, in ferroelectric capacitors the read-out of the polarization charge is destructive. The functionality of the targeted memory should be based on resistive switching. In inorganic ferroelectrics conductivity and ferroelectricity cannot be tuned independently. The challenge is to develop a storage medium in which the favourable properties of ferroelectrics such as bistability and non-volatility can be combined with the beneficial properties provided by semiconductors such as conductivity and rectification. Here we present an integrated solution by blending semiconducting and ferroelectric polymers into phase-separated networks. The polarization field of the ferroelectric modulates the injection barrier at the semiconductor-metal contact. The combination of ferroelectric bistability with (semi)conductivity and rectification allows for solution-processed non-volatile memory arrays with a simple cross-bar architecture that can be read out non-destructively. The concept of an electrically tunable injection barrier as presented here is general and can be applied to other electronic devices such as light-emitting diodes with an integrated on/off switch.

High-Performance Flexible Hybrid Field-Effect Transistors Based on Cellulose Fiber Paper

Abstract: In this letter, we report for the first time the use of a sheet of cellulose-fiber-based paper as the dielectric layer used in oxide-based semiconductor thin-film field-effect transistors (FETs). In this new approach, we are using the cellulose-fiber-based paper in an ldquointerstraterdquo structure since the device is built on both sides of the cellulose sheet. Such hybrid FETs present excellent operating characteristics such as high channel saturation mobility,(> 30 cm2 / vs drain-source current on/off modulation ratio of approximately 104, near-zero threshold voltage, enhancement n-type operation, and subthreshold gate voltage swing of 0.8 V/decade. The cellulose-fiber-based paper FETs' characteristics have been measured in air ambient conditions and present good stability, after two months of being processed. The obtained results outpace those of amorphous Si thin-film transistors (TFTs) and rival with the same oxide-based TFTs produced on either glass or crystalline silicon substrates. The compatibility of these devices with large-scale/large-area deposition techniques and low-cost substrates as well as their very low operating bias delineates this as a promising approach to attain high-performance disposable electronics like paper displays, smart labels, smart packaging, RFID, and point-of-care systems for self-analysis in bioapplications, among others.

Thiophene Polymer Semiconductors for Organic Thin‐Film Transistors

Abstract: Printed organic thin-film transistors (OTFTs) have received great interests as potentially low-cost alternative to silicon technology for application in large-area, flexible, and ultra-low-cost electronics. One of the critical materials for TFTs is semiconductor, which has a dominant impact on the transistor properties. We review here the structural studies and design of thiophene-based polymer semiconductors with respect to solution processability, ambient stability, molecular self-organization, and field-effect transistor properties for OTFT applications. We show that through judicial monomer design, delicately controlled pi-conjugation, and strategically positioned pendant side-chain distribution, novel solution-processable thiophene polymer semiconductors with excellent self-organization ability to form extended lamellar pi-stacking orders can be developed. OTFTs using semiconductors of this nature processed in ambient conditions have provided excellent field-effect transistor properties.

Organic n-Channel Transistors Based on Core-Cyanated Perylene Carboxylic Diimide Derivatives

Abstract: Five core-cyanated perylene carboxylic diimides end-functionalized with fluorine-containing linear and cyclic substituents have been synthesized and employed in the fabrication of air-stable n-channel organic thin-film field-effect transistors with carrier mobilities up to 0.1 cm 2 /Vs. The relationships between molecular structure, thin-film morphology, substrate temperature during vacuum deposition, transistor performance, and air stability have been investigated. Our experiments led us to conclude that the role of the fluorine functionalization in the air-stable n-channel operation of the transistors is different than previously thought.

n-Type behavior of graphene supported on Si/SiO(2) substrates.

Abstract: Results are presented from an experimental and theoretical study of the electronic properties of back-gated graphene field effect transistors (FETs) on Si/SiO2 substrates. The excess charge on the graphene was observed by sweeping the gate voltage to determine the charge neutrality point in the graphene. Devices exposed to laboratory environment for several days were always found to be initially p-type. After ∼20 h at 200 °C in ∼5 × 10−7 Torr vacuum, the FET slowly evolved to n-type behavior with a final excess electron density on the graphene of ∼4 × 1012 e/cm2. This value is in excellent agreement with our theoretical calculations on SiO2, where we have used molecular dynamics to build the SiO2 structure and then density functional theory to compute the electronic structure. The essential theoretical result is that the SiO2 has a significant surface state density just below the conduction band edge that donates electrons to the graphene to balance the chemical potential at the interface. An electrostati...

Graphene Nanoribbon Tunnel Transistors

Abstract: A graphene nanoribbon (GNR) tunnel field-effect transistor (TFET) is proposed and modeled analytically. Ribbon widths between 3 and 10 nm are considered to effect energy bandgaps in the range of 0.46 to 0.14 eV. It is shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing. The transistor achieves 800 muA/mum on -state current and 26 pA/mum off-state current, with an effective subthreshold swing of 0.19 mV/dec. Compared to a projected 2009 n MOSFET, the GNR TFET can provide 5times higher speed, 20times lower dynamic power, and 280 000times lower off-state power dissipation. The high performance of GNR TFETs results from their narrow bandgaps and their 1-D nature.

Top-gated graphene field-effect-transistors formed by decomposition of SiC

Abstract: Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal arrangement of carbon atoms with the correct lattice vectors, observed by high-resolution scanning tunneling microscopy, confirms the formation of multiple graphene layers on top of the SiC substrates. The observation of n-type and p-type transition further verifies Dirac Fermions’ unique transport properties in graphene layers. The measured electron and hole mobilities on these fabricated graphene FETs are as high as 5400 and 4400cm2∕Vs, respectively, which are much larger than the corresponding values from conventional SiC or silicon.

HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE

Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal- containing gate conductor 30 has gate corners 31 located at a base segment of the metal- containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30. The gate spacer 36 is located upon an upper surface of both the gate dielectric 18 and the high-k gate dielectric that is present at the gate corners 31.

Pentacene-based organic field-effect transistors

Abstract: Organic field-effect transistors (FETs) have attracted considerable attention because of their potential for realizing large-area, mechanically flexible, lightweight and low-cost devices. Pentacene, which is a promising material for organic FETs, has been intensely studied. This article reviews the basic properties of pentacene films and crystals, and the characteristics of pentacene FETs fabricated under various conditions, including our recent achievement of low-voltage operating high-mobility FETs. The basic properties include the crystal polymorph, the band structure and the effective mass. These data have been used for discussion of carrier transport and mobility in pentacene films. The characteristics of pentacene FETs generally depend on the conditions of the pentacene film and the gate-dielectric surface. The dependences are summarized in the article. In addition, liquid-crystal displays and organic light-emitting device arrays using pentacene FETs are reviewed as applications of organic FETs, and complementary metal–oxide–semiconductor circuits using our low-voltage operating FETs are also shown.

High current density in light-emitting transistors of organic single crystals.

Abstract: We measured the external electroluminescence quantum efficiency (eta(ext)) in light-emitting field-effect transistors (LETs) made of organic single crystals and found that, in the ambipolar transport region, eta(ext) is not degraded up to several hundreds A/cm(2) current-density range, which is 2 orders of magnitude larger than that achieved in conventional organic light-emitting diodes. The present result indicates the single-crystal organic LET is a promising device structure that is free from various kinds of nonradiative losses such as exciton dissociation near electrodes and exciton annihilations.

GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

Abstract: A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current–gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.

Air-assisted high-performance field-effect transistor with thin films of picene.

Abstract: A field-effect transistor (FET) with thin films of picene has been fabricated on SiO2 gate dielectric. The FET showed p-channel enhancement-type FET characteristics with the field-effect mobility, μ, of 1.1 cm2 V−1 s−1 and the on−off ratio of >105. This excellent device performance was realized under atmospheric conditions. The μ increased with an increase in temperature, and the FET performance was improved by exposure to air or O2 for a long time. This result implies that this device is an air (O2)-assisted FET. The FET characteristics are discussed on the basis of structural topography and the energy diagram of picene thin films.

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

Abstract: We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx, gate dielectrics.

High-mobility, low-power, and fast-switching organic field-effect transistors with ionic liquids

Abstract: We report high-mobility rubrene single-crystal field-effect transistors with ionic-liquid (IL) electrolytes used for gate dielectric layers. As the result of fast ionic diffusion to form electric double layers, their capacitances remain more than 1μF∕cm2 even at 0.1MHz. With high carrier mobility of 1.2cm2∕Vs in the rubrene crystal, pronounced current amplification is achieved at the gate voltage of only 0.2V, which is two orders of magnitude smaller than that necessary for organic thin-film transistors with dielectric gate insulators. The results demonstrate that the IL/organic semiconductor interfaces are suited to realize low-power and fast-switching field-effect transistors without sacrificing carrier mobility in forming the solid/liquid interfaces.

Vertical GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistors on GaN Bulk Substrates

Abstract: Completely vertical trench gate metal oxide semiconductor field-effect transistors (MOSFETs) have been produced using gallium nitride (GaN) for the first time. These MOSFETs exhibited enhancement-mode operation with a threshold voltage of 3.7 V and an on-resistance of 9.3 mΩcm2. The channel mobility was estimated to be 131 cm2/(Vs) when all the resistances except for that of the channel are considered. Such structures, which satisfy the key words "vertical", "trench gate", and "MOSFET", will enable us to fabricate practical GaN-based power switching devices.

Surface‐Dominated Transport Properties of Silicon Nanowires

Abstract: Surface effects are widely recognized to significantly influence the properties of nanostructures, although the detailed mechanisms are rarely studied and unclear. Herein we report for the first time a quantitative evaluation of the surface-related contributions to transport properties in nanostructures by using Si nanowires (NWs) as a paradigm. Critical to this study is the capability of synthesizing SiNWs with predetermined conduction type and carrier concentration from Si wafer of known properties using the recently developed metal-catalyzed chemical etching method. Strikingly, the conductance of p-type SiNWs is is substantively larger in air than that of the original wafer, is sensitive to humidity and volatile gases, and thinner wires show higher conductivity. Further, SiNW-based field-effect transistors (FETs) show NWs to have a hole concentration two orders of magnitude higher than the original wafer. In vacuum, the conductivity of SiNWs dramatically decreases, whereas hole mobility increases. The device performances are further improved by embedding SiNW FETs in 250 nm SiO 2, which insulates the devices from atmosphere and passivates the surface defects of NWs. Owing to the strong surface effects, n-type SiNWs even change to exhibit p-type characteristics. The totality of the results provides definitive confirmation that the electrical characteristics of SiNWs are dominated by surface states. A model based on surface band bending and carrier scattering caused by surface states is proposed to interpret experimental results. The phenomenon of surface-dependent transport properties should be generic to all nanoscale structures, and is significant for nanodevice design for sensor and electronic applications.

High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

Abstract: This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.

Nonvolatile Switching in Graphene Field-Effect Devices

Abstract: The absence of a band gap in graphene restricts its straightforward application as a channel material in field-effect transistors. In this letter, we report on a new approach to engineer a band gap in graphene field-effect devices (FEDs) by controlled structural modification of the graphene channel itself. The conductance in the FEDs is switched between a conductive ldquoon-staterdquo and an insulating ldquooff-staterdquo with more than six orders of magnitude difference in conductance. Above a critical value of an electric field applied to the FED gate under certain environmental conditions, a chemical modification takes place to form insulating graphene derivatives. The effect can be reversed by electrical fields of opposite polarity or short current pulses to recover the initial state. These reversible switches could potentially be applied to nonvolatile memories and novel neuromorphic processing concepts.

Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates

Abstract: As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an inverter and competing with the MOSFET. We have investigated the heterostructure TFET with respect to complementarity based on our semi-analytical model, and we propose the InxGa1 - xAs-source silicon-TFET as p-TFET. This design is particularly applicable to nanowire-based transistor architectures. We discuss the complementarity of the I-V curves, and we analyze the threshold voltage behavior of the complementary TFETs.

Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications

Abstract: The device physics and electrical characteristics of the germanium (Ge) tunneling field-effect transistor (TFET) are investigated for high performance and low power logic applications using two dimensional device simulation. Due to the high band-to-band tunneling rate of Ge as compared to Si, the Ge TFET suffers from excessive off-state leakage current Ioff despite its higher on-state current Ion. It is shown for the first time that the high off-state leakage due to the drain-side tunneling in the Ge TFET can be effectively suppressed by controlling the drain doping concentration. A lower drain doping concentration reduces the electric field and increases the tunneling barrier width in the drain side, giving a significantly reduced off-state leakage. To increase Ion with a steeper subthreshold swing S, source doping concentration is increased to reduce the bandgap and narrow the tunneling width. Device design and physics detailing the impact of drain and source engineering on the performance of Ge TFET ar...