Showing papers on "Field-effect transistor published in 2010"

100-GHz Transistors from Wafer-Scale Epitaxial Graphene

Abstract: The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length.

Graphene photodetectors for high-speed optical communications

Abstract: Although silicon has dominated solid-state electronics for more than four decades, a variety of other materials are used in photonic devices to expand the wavelength range of operation and improve performance. For example, gallium-nitride based materials enable light emission at blue and ultraviolet wavelengths1, and high index contrast silicon-on-insulator facilitates ultradense photonic devices2,3. Here, we report the first use of a photodetector based on graphene4,5, a two-dimensional carbon material, in a 10 Gbit s−1 optical data link. In this interdigitated metal–graphene–metal photodetector, an asymmetric metallization scheme is adopted to break the mirror symmetry of the internal electric-field profile in conventional graphene field-effect transistor channels6,7,8,9, allowing for efficient photodetection. A maximum external photoresponsivity of 6.1 mA W−1 is achieved at a wavelength of 1.55 µm. Owing to the unique band structure of graphene10,11 and extensive developments in graphene electronics12,13 and wafer-scale synthesis13, graphene-based integrated electronic–photonic circuits with an operational wavelength range spanning 300 nm to 6 µm (and possibly beyond) can be expected in the future. A graphene-based photodetector with unprecedented photoresponsivity and the ability to perform error-free detection of 10 Gbit s−1s data streams is demonstrated. The results suggest that graphene-based photonic devices have a bright future in telecommunications and other optical applications.

Nanowire transistors without junctions

Abstract: All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

Graphene field-effect transistors with high on/off current ratio and large transport band gap at room temperature.

Abstract: Graphene is considered to be a promising candidate for future nanoelectronics due to its exceptional electronic properties. Unfortunately, the graphene field-effect transistors (FETs) cannot be turned off effectively due to the absence of a band gap, leading to an on/off current ratio typically around 5 in top-gated graphene FETs. On the other hand, theoretical investigations and optical measurements suggest that a band gap up to a few hundred millielectronvolts can be created by the perpendicular E-field in bilayer graphenes. Although previous carrier transport measurements in bilayer graphene transistors did indicate a gate-induced insulating state at temperatures below 1 K, the electrical (or transport) band gap was estimated to be a few millielectronvolts, and the room temperature on/off current ratio in bilayer graphene FETs remains similar to those in single-layer graphene FETs. Here, for the first time, we report an on/off current ratio of around 100 and 2000 at room temperature and 20 K, respectively, in our dual-gate bilayer graphene FETs. We also measured an electrical band gap of >130 and 80 meV at average electric displacements of 2.2 and 1.3 V nm(-1), respectively. This demonstration reveals the great potential of bilayer graphene in applications such as digital electronics, pseudospintronics, terahertz technology, and infrared nanophotonics.

Wafer-Scale Synthesis and Transfer of Graphene Films

Abstract: We developed means to produce wafer scale, high-quality graphene films as large as 3 in. wafer size on Ni and Cu films under ambient pressure and transfer them onto arbitrary substrates through instantaneous etching of metal layers. We also demonstrated the applications of the large-area graphene films for the batch fabrication of field-effect transistor (FET) arrays and stretchable strain gauges showing extraordinary performances. Transistors showed the hole and electron mobilities of the device of 1100 ± 70 and 550 ± 50 cm2/(V s) at drain bias of −0.75 V, respectively. The piezo-resistance gauge factor of strain sensor was ∼6.1. These methods represent a significant step toward the realization of graphene devices in wafer scale as well as application in optoelectronics, flexible and stretchable electronics.

High-k organic, inorganic, and hybrid dielectrics for low-voltage organic field-effect transistors.

Abstract: 2.2. Interface Trapping Effects 211 3. High-k Dielectric Materials for OFETs 212 3.1. Inorganic Dielectrics 212 3.1.1. Aluminum Oxide 213 3.1.2. Tantalum Oxide 215 3.1.3. Titanium Dioxide 216 3.1.4. Hafnium Dioxide 217 3.1.5. Zirconium Dioxide 218 3.1.6. Cerium Dioxide 218 3.2. Organic Dielectrics 218 3.2.1. Polymer Dielectrics 218 3.2.2. Self-Assembled Monoand Multilayers 225 3.3. Hybrid Dielectrics 227 3.3.1. Polymeric-Nanoparticle Composites 227 3.3.2. Inorganic-Organic Bilayers 232 3.3.3. Hybrid Solid Polymer Electrolytes 235 4. Summary 235 5. Acknowledgments 236 6. References 236

Controllable N-Doping of Graphene

Abstract: Opening and tuning an energy gap in graphene are central to many electronic applications of graphene. Here we report N-doped graphene obtained by NH3 annealing after N+-ion irradiation of graphene samples. First, the evolution of the graphene microstructure was investigated following N+-ion irradiation at different fluences using Raman spectroscopy, showing that defects were introduced in plane after irradiation and then restored after annealing in N2 or in NH3. Auger electron spectroscopy (AES) of the graphene annealed in NH3 after irradiation showed N signal, however, no N signal was observed after annealing in N2. Last, the field-effect transistor (FET) was fabricated using N-doped graphene and monitored by the source−drain conductance and back-gate voltage (Gsd−Vg) curves in the measurement. The transport property changed compared to that of the FET made by intrinsic graphene, that is, the Dirac point position moved from positive Vg to negative Vg, indicating the transition of graphene from p-type to ...

Subthreshold Regime has the Optimal Sensitivity for Nanowire FET Biosensors

Abstract: Nanowire field-effect transistors (NW-FETs) are emerging as powerful sensors for detection of chemical/biological species with various attractive features including high sensitivity and direct electrical readout. Yet to date there have been limited systematic studies addressing how the fundamental factors of devices affect their sensitivity. Here we demonstrate that the sensitivity of NW-FET sensors can be exponentially enhanced in the subthreshold regime where the gating effect of molecules bound on a surface is the most effective due to the reduced screening of carriers in NWs. This principle is exemplified in both pH and protein sensing experiments where the operational mode of NW-FET biosensors was tuned by electrolyte gating. The lowest charge detectable by NW-FET sensors working under different operational modes is also estimated. Our work shows that optimization of NW-FET structure and operating conditions can provide significant enhancement and fundamental understanding for the sensitivity limits ...

Performance estimation of junctionless multigate transistors

Abstract: This paper describes the simulation of the electrical characteristics of a new transistor concept called the ‘‘Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications.

GaN Power Transistors on Si Substrates for Switching Applications

Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were examined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance (Ron) and a high breakdown voltage (Vb).

GaN Power Transistors on Si Substrates for Switching Applications Hybrid MOS-FET transistor devices with low on-resistance, high hold-voltages and high breakdown voltage promise to provide high-power, low-loss operation for switching applications.

Abstract: In this paper, GaN power transistors on Si substrates for power switching application are reported. GaN heterojunction field-effect transistor (HFET) structure on Si is an important configuration in order to realize a low loss and high power devices as well as one of the cost-effective solutions. Current collapse phenomena are discussed for GaN-HFETs on Si substrate, resulting in suppression of the current collapse due to using the conducting Si substrate. Furthermore, attempts for normally off GaN-FETs were exam- ined. A hybrid metal-oxide-semiconductor HFET structure is a promising candidate for obtaining devices with a lower on-resistance ðRonÞ and a high breakdown voltage ðVbÞ.

Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors

Abstract: Compound semiconductor materials such as gallium arsenide and indium arsenide have outstanding electronic properties, but are costly to process and cannot, on their own, compete with silicon when it comes to low-cost fabrication. But as the relentless miniaturization of silicon electronics is reaching its limits, an alternative route of enhanced device performance is becoming more attractive: the integration of compound semiconductors within silicon. Ali Javey and colleagues now present a promising new concept to integrate ultrathin layers of single-crystal indium arsenide on silicon-based substrates with an epitaxial transfer method, a technique borrowed from large-area optoelectronics. With this technique, involving the use of an elastomeric stamp to lift off indium arsenide nanowires and transfer them to a silicon-based substrate, the authors fabricate thin film transistors with excellent device performance. A potential route to enhancing the performance of electronic devices is to integrate compound semiconductors, which have superior electronic properties, within silicon, which is cheap to process. These authors present a promising new concept to integrate ultrathin layers of single-crystal indium arsenide on silicon-based substrates with an epitaxial transfer method borrowed from large-area optoelectronics. With this technique, the authors fabricate thin-film transistors with excellent device performance. Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance1,2,3,4,5,6,7,8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied7,9,10: such devices combine the high mobility of III–V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored9,11,12,13—but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO2 substrates. As a parallel with silicon-on-insulator (SOI) technology14, we use ‘XOI’ to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO x layer (~1 nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6 mS µm−1 at a drain–source voltage of 0.5 V, with an on/off current ratio of greater than 10,000.

High-Temperature Performance of Silicon Junctionless MOSFETs

Abstract: This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.

Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

Abstract: A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal-oxide-semiconductor field-effect transistor due to its immunity to short-channel effects. However, TFETs have suffered from low on-current, severe ambipolar behavior, and gradual transition between on- and off -states. To address those issues, the authors have proposed hetero-gate-dielectric TFETs. The proposed device enhances on-current, suppresses ambipolar behavior, and makes abrupt on-off transition by replacing the source-side gate insulator with a high-k material, which induces a local minimum of the conduction band edge at the tunneling junction.

A Crystal-Engineered Hydrogen-Bonded Octachloroperylene Diimide with a Twisted Core: An n-Channel Organic Semiconductor

Abstract: The appropriate arrangement of organic semiconductors in the solid state is decisive for efficient charge-carrier transport between source and drain electrodes in organic thin-film transistors (OTFTs). However, the still unsolved challenges in crystal engineering mean that there are only few examples where the packing of p-conjugated semiconductors can be controlled by means of rational design concepts to avoid the most common herringbone p-stacking motif (Figure 1a). An outstanding example is provided by the

Nernst limit in dual-gated Si-nanowire FET sensors.

Abstract: Field effect transistors (FETs) are widely used for the label-free detection of analytes in chemical and biological experiments. Here we demonstrate that the apparent sensitivity of a dual-gated silicon nanowire FET to pH can go beyond the Nernst limit of 60 mV/pH at room temperature. This result can be explained by a simple capacitance model including all gates. The consistent and reproducible results build to a great extent on the hysteresis- and leakage-free operation. The dual-gate approach can be used to enhance small signals that are typical for bio- and chemical sensing at the nanoscale.

Origin of NBTI variability in deeply scaled pFETs

Abstract: The similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs. A SPICE-based simplified channel percolation model is devised to confirm this behavior. The overall device-to-device ΔV th distribution following NBTI stress is argued to be a convolution of exponential distributions of uncorrelated individual charged defects Poisson-distributed in number. An analytical description of the total NBTI threshold voltage shift distribution is derived, allowing, among other things, linking its first two moments with the average number of defects per device.

High-mobility ambipolar transistors and high-gain inverters from a donor-acceptor copolymer semiconductor.

Abstract: Ambipolar organic field-effect transistors (OFETs), which are capable of both p- and n-channel operations, are gaining attention as an alternative approach to mimicking complementary metal-oxide semiconductor (CMOS) digital integrated circuits for achieving high-performance and cost-effective circuits in organic electronics. [1‐13] Low power dissipation and high performance are some of the major advantages of CMOS technology over non-complementary ones. [14] Power consumption is minimized in CMOS circuits because the component transistors are selectively turned on only when the circuit is switching, otherwise they are off at the steady state. The better performance of a CMOS circuit in terms of sharp switching and high noise immunity arises because every elemental transistor actively contributes to the function of the circuit. [14] Most efforts towards CMOS-like circuits in organic electronics have focused on utilizing distinct p- and n-type semiconductors. [1,15] However, the necessity of lateral patterning of semiconductors in CMOS circuits makes device fabrication on a common substrate a very complex process. Ambipolar OFETs represent an approach to high-performance CMOS-like circuits that minimize patterning and complex fabrication processes. [1] Ambipolar transistors are also of interest in fundamental studies of charge transport in organic semiconductors [1,6,16] as well as the development of efficient light-emitting transistors. [8,17‐21]

Fin-like field effect transistor (finfet) device and method of manufacturing same

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed on a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

Fin-like field effect transistor (FinFET) device and method of manufacturing same

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.

Graphene-Based Ambipolar RF Mixers

Abstract: The combination of the unique properties of graphene with new device concepts and nanotechnology can overcome some of the main limitations of traditional electronics in terms of maximum frequency, linearity, and power dissipation. In this letter, we demonstrate the use of the ambipolar-transport properties of graphene for the fabrication of a new kind of RF mixer device. Due to the symmetrical ambipolar conduction in graphene, graphene-based mixers can effectively suppress odd-order intermodulations and lead to lower spurious emissions in the circuit. The mixer operation was demonstrated at a frequency of 10 MHz using graphene grown by chemical vapor deposition on a Ni film and then transferred to an insulating substrate. The maximum operating frequency was limited by the device geometry and the measurement setup, and a high-quality factor was observed with a third-order intercept point of +13.8 dBm.

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Abstract: Organic field-effect transistor (FET) memory is an emerging technology with the potential to realize light-weight, low-cost, flexible charge storage media. Here, solution-processed poly[9,9-dioctylfluorenyl-2,7-diyl]-co-(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top-gate/bottom-contact device configuration is reported. A reversible shift in the threshold voltage (V Th ) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross-linked poly(4-vinylphenol). The F8T2 NFGM showed relatively high field-effect mobility (μ FET ) (0.02 cm 2 V -1 s -1 ) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10 4 ) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top-gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.

Ferroelectric field effect transistors for memory applications.

Abstract: The non-volatile polarization of a ferroelectric is a promising candidate for digital memory applications. Ferroelectric capacitors have been successfully integrated with silicon electronics, where the polarization state is read out by a device based on a field effect transistor configuration. Coupling the ferroelectric polarization directly to the channel of a field effect transistor is a long-standing research topic that has been difficult to realize due to the properties of the ferroelectric and the nature of the interface between the ferroelectric and the conducting channel. Here, we report on the fabrication and characterization of two promising capacitor-less memory architectures.

It's time to reinvent the transistor!

Abstract: A breakthrough in materials could refresh and sustain the information technology revolution.

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

Abstract: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions

Abstract: This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The depletion regions induced inside the source and drain are included in the solution, and we show that these regions become critical when scaling the device length. The fringing field effect from the gates on these regions is also included. The validity of the model is tested for devices scaled to 10-nm length with SiO2 and high-? dielectrics by comparison to 2-D finite-element simulations.

Flexible low-voltage organic transistors and circuits based on a high-mobility organic semiconductor with good air stability.

Abstract: Flexible transistors and circuits based on dinaphtho-[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT), a conjugated semiconductor with a large ionization potential (5.4 eV), are reported. The transistors have a mobility of 0.6 cm(2) V-1 s(-1) and the ring oscillators have a stage delay of 18 mu s. Due to the excellent stability of the semiconductor, the devices and circuits maintain 50% of their initial performance for a period of 8 months in ambient air.

Modeling of graphene metal-oxide-semiconductor field-effect transistors with gapless large-area graphene channels

Abstract: A quasianalytical modeling approach for graphene metal-oxide-semiconductor field-effect transistors (MOSFETs) with gapless large-area graphene channels is presented. The model allows the calculation of the I-V characteristics, the small-signal behavior, and the cutoff frequency of graphene MOSFETs. It applies a correct formulation of the density of states in large-area graphene to calculate the carrier-density-dependent quantum capacitance, a steady-state velocity-field characteristics with soft saturation to describe the carrier transport, and takes the source/drain series resistances into account. The modeled drain currents and transconductances show very good agreement with experimental data taken from the literature {Meric et al., [Nat. Nanotechnol. 3, 654 (2008)] and Kedzierski et al., [IEEE Electron Device Lett. 30, 745 (2009)]}. In particular, the model properly reproduces the peculiar saturation behavior of graphene MOSFETs with gapless channels.

In Quest of the “Next Switch”: Prospects for Greatly Reduced Power Dissipation in a Successor to the Silicon Field-Effect Transistor

Abstract: Reduced power dissipation relative to the field-effect transistor (FET) is a key attribute that should be possessed by any device that has a chance of supplanting the FET as the ubiquitous building block for complex digital logic. We outline the possible physical approaches to achieving this attribute, and illustrate these approaches by citing current exploratory device research. We assess the value of the key exploratory research objectives of the semiconductor industry-sponsored Nanoelectronics Research Initiative (NRI) in the light of this pressing need to reduce dissipation in future digital logic devices.