Showing papers on "Field-effect transistor published in 2011"

Tunnel field-effect transistors as energy-efficient electronic switches

Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

How Good Can Monolayer MoS2 Transistors Be

Abstract: Monolayer molybdenum disulfide (MoS2), unlike its bulk form, is a direct band gap semiconductor with a band gap of 1.8 eV. Recently, field-effect transistors have been demonstrated experimentally using a mechanically exfoliated MoS2 monolayer, showing promising potential for next generation electronics. Here we project the ultimate performance limit of MoS2 transistors by using nonequilibrium Green’s function based quantum transport simulations. Our simulation results show that the strength of MoS2 transistors lies in large ON–OFF current ratio (>1010), immunity to short channel effects (drain-induced barrier lowering ∼10 mV/V), and abrupt switching (subthreshold swing as low as 60 mV/decade). Our comparison of monolayer MoS2 transistors to the state-of-the-art III–V materials based transistors, reveals that while MoS2 transistors may not be ideal for high-performance applications due to heavier electron effective mass (m* = 0.45m0) and a lower mobility, they can be an attractive alternative for low power...

Wafer-Scale Graphene Integrated Circuit

Abstract: A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

Nature of electronic states in atomically thin MoS₂ field-effect transistors.

Abstract: We present low-temperature electrical transport experiments in five field-effect transistor devices consisting of monolayer, bilayer, and trilayer MoS(2) films, mechanically exfoliated onto Si/SiO(2) substrate. Our experiments reveal that the electronic states in all films are localized well up to room temperature over the experimentally accessible range of gate voltage. This manifests in two-dimensional (2D) variable range hopping (VRH) at high temperatures, while below ∼30 K, the conductivity displays oscillatory structures in gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T(0)) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges in the substrate is the dominant source of disorder in MoS(2) field-effect devices, which leads to carrier localization, as well.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Development of hafnium based high-k materials—A review

Abstract: The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor field effect transistor is considered one of the most dramatic advances in materials science since the invention of silicon based transistors. Metal oxides are superior to SiO 2 in terms of their higher dielectric constants that enable the required continuous down-scaling of the electrical thickness of the dielectric layer while providing a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. Over the last decade, hafnium based materials have emerged as the designated dielectrics for future generation of nano-electronics with a gate length less than 45 nm, though there exists no consensus on the exact composition of these materials, as evolving device architectures dictate different considerations when optimizing a gate dielectric material. In addition, the implementation of a non-silicon based gate dielectric means a paradigm shift from diffusion based thermal processes to atomic layer deposition processes. In this report, we review how HfO 2 emerges from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques. Then we use specific examples to discuss the evolution in designing hafnium based materials, from binary to complex oxides and to non-oxide forms as gate dielectric, metal gates and diffusion barriers. To address the impact of these hafnium based materials, their interfaces with silicon as well as a variety of semiconductors are discussed. Finally, the integration issues are highlighted, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning, which are essential to realize future generations of devices using hafnium-based high- k materials.

Fundamental Theory of Piezotronics

Abstract: Due to polarization of ions in crystals with noncentral symmetry, such as ZnO, GaN, and InN, a piezoelectric potential (piezopotential) is created in the crystal when stress is applied. Electronics fabricated using the inner-crystal piezopotential as a gate voltage to tune or control the charge transport behavior across a metal/semiconductor interface or a p-n junction are called piezotronics. This is different from the basic design of complimentary metal oxide semiconductor (CMOS) field-effect transistors and has applications in force and pressure triggered or controlled electronic devices, sensors, microelectromechanical systems (MEMS), human-computer interfacing, nanorobotics, and touch-pad technologies. Here, the theory of charge transport in piezotronic devices is investigated. In addition to presenting the formal theoretical frame work, analytical solutions are presented for cases including metal-semiconductor contact and p-n junctions under simplified conditions. Numerical calculations are given for predicting the current-voltage characteristics of a general piezotronic transistor: metal-ZnO nanowire-metal device. This study provides important insight into the working principles and characteristics of piezotronic devices, as well as providing guidance for device design.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

1200-V Normally Off GaN-on-Si Field-Effect Transistors With Low Dynamic on -Resistance

Abstract: This letter reports high-voltage GaN field-effect transistors fabricated on Si substrates. A halide-based plasma treatment was performed to enable normally off operation. Atomic layer deposition of Al2O3 gate insulator was adopted to reduce the gate leakage current. Incorporation of multiple field plates, with one field plate connected to the gate electrode and two field plates connected to the source electrode successfully enabled a high breakdown voltage of 1200 V and low dynamic on-resistance at high-voltage operation.

Broadband terahertz imaging with highly sensitive silicon CMOS detectors

Abstract: This paper investigates terahertz detectors fabricated in a low-cost 130 nm silicon CMOS technology. We show that the detectors consisting of a nMOS field effect transistor as rectifying element and an integrated bow-tie coupling antenna achieve a record responsivity above 5 kV/W and a noise equivalent power below 10 pW/Hz(0.5) in the important atmospheric window around 300 GHz and at room temperature. We demonstrate furthermore that the same detectors are efficient for imaging in a very wide frequency range from ~0.27 THz up to 1.05 THz. These results pave the way towards high sensitivity focal plane arrays in silicon for terahertz imaging.

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

Abstract: This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (I D ) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase I D by more than 20X.

Accessing the transport properties of graphene and its multilayers at high carrier density

Abstract: We present a comparative study of high carrier density transport in mono-, bi-, and trilayer graphene using electric double-layer transistors to continuously tune the carrier density up to values exceeding 10(14) cm(-2). Whereas in monolayer the conductivity saturates, in bi- and trilayer filling of the higher-energy bands is observed to cause a nonmonotonic behavior of the conductivity and a large increase in the quantum capacitance. These systematic trends not only show how the intrinsic high-density transport properties of graphene can be accessed by field effect, but also demonstrate the robustness of ion-gated graphene, which is crucial for possible future applications.

Probing charge transfer at surfaces using graphene transistors.

Abstract: Graphene field effect transistors (FETs) are extremely sensitive to gas exposure. Charge transfer doping of graphene FETs by atmospheric gas is ubiquitous but not yet understood. We have used graphene FETs to probe minute changes in electrochemical potential during high-purity gas exposure experiments. Our study shows quantitatively that electrochemistry involving adsorbed water, graphene, and the substrate is responsible for doping. We not only identify the water/oxygen redox couple as the underlying mechanism but also capture the kinetics of this reaction. The graphene FET is highlighted here as an extremely sensitive potentiometer for probing electrochemical reactions at interfaces, arising from the unique density of states of graphene. This work establishes a fundamental basis on which new electrochemical nanoprobes and gas sensors can be developed with graphene.

Electrical Detection of Metal Ions Using Field-Effect Transistors Based on Micropatterned Reduced Graphene Oxide Films

Abstract: The electrical property of graphene is highly sensitive to its local environment, which makes graphene an ideal channel material in electronic sensors. Reduced graphene oxide (rGO) has been used as the desirable alternative to the pristine graphene due to its low-cost, solution-processable, and scalable production. In this paper, we present a field-effect transistor sensor using micropatterned, protein-functionalized rGO film as the conducting or sensing channel. Such a nanoelectronic sensor is able to detect various metal ions in real-time with high sensitivity.

A polysaccharide bioprotonic field-effect transistor

Abstract: In nature, electrical signalling occurs with ions and protons, rather than electrons. Artificial devices that can control and monitor ionic and protonic currents are thus an ideal means for interfacing with biological systems. Here we report the first demonstration of a biopolymer protonic field-effect transistor with proton-transparent PdH(x) contacts. In maleic-chitosan nanofibres, the flow of protonic current is turned on or off by an electrostatic potential applied to a gate electrode. The protons move along the hydrated maleic-chitosan hydrogen-bond network with a mobility of ~4.9×10(-3) cm(2) V(-1) s(-1). This study introduces a new class of biocompatible solid-state devices, which can control and monitor the flow of protonic current. This represents a step towards bionanoprotonics.

Graphene Transistor Arrays for Recording Action Potentials from Electrogenic Cells

Abstract: The development of the future generation of neuroprosthetic devices will require the advancement of novel solid-state sensors and actuators with a further improvement in the signal detection capability, a superior stability in biological environments, and a more suitable compatibility with living tissue. To date, interfacing of living cells and tissue with solid-state electronic devices has mainly been based on conventional silicon technology, in particular using Si metal-oxide-semiconductor fi eld-effect transistor (MOSFET) structures. [ 1 ] However, some of the drawbacks associated with this technology, such as its limited stability in aqueous environments [ 2 ] and a relatively high electrical noise, [ 3 ] have triggered the study of alternative materials and technologies. [ 4–11 ] In this respect, solution-gated fi eldeffect transistors (SGFETs) based on Si-nanowires, [ 4 ] AlGaN/ GaN heterostructures, [ 5 ] H-terminated diamond, [ 6 , 7 ] carbon nanotubes, [ 8 ] and, more recently, graphene [ 9–11 ] have been investigated as sensing devices. Among these materials, graphene is a particularly attractive candidate for bioelectronic applications, due to its remarkable physical and chemical properties. The extremely high charge carrier mobility in graphene [ 12 ] leads to a fi eld-effect transistor (FET) performance that is superior to most known semiconductors. [ 13 ] In addition, graphene is known to possess good chemical stability [ 14 ] and biocompatibility, [ 15 ] which is crucial not only for integration with biological systems, but also for the operation of fi eld-effect devices without a protective dielectric layer. Furthermore, the facile integration of graphene electronics with fl exible substrates paves the way for the development of fl exible devices, an important requirement for the design of biomedical implants with reduced tissue damage and scarring. [ 16 ] The use of graphene-based solutiongated fi eld-effect transistors (G-SGFETs) for the detection of cell signals has already been demonstrated on a fundamental level by using a single transistor on exfoliated graphene. [ 8 ] Despite this promising preliminary result, a successful graphene-based technology for the applications envisioned above requires the demonstration of arrays of graphene transistors, which can

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

Abstract: We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

Abstract: Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.

Theory of the Junctionless Nanowire FET

Abstract: In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent on-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.

BN/Graphene/BN Transistors for RF Applications

Abstract: In this letter, we demonstrate the first BN/graphene/BN field-effect transistor for RF applications. This device structure can preserve the high mobility and the high carrier velocity of graphene, even when it is sandwiched between a substrate and a gate dielectric, and is hence very promising to enable the next generation of high-frequency graphene RF electronics.

Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors

Abstract: We report the discovery of ferroelectricity in crystalline hafnium silicon oxide If HfO 2 based thin films, at a composition where the tetragonal phase is not yet stable, are crystallized in presence of a cap, the formation of an orthorhombic phase is observed o-HfO 2 shows a piezoelectric response, while a polarization measurements exhibit a remanent polarization above 10 µC/cm2 at a coercive field of 1 MV/cm, confirming this phase to be ferroelectric Transistors fabricated with this material exhibit a permanent and switchable shift of the threshold voltage, allowing the realization of CMOS-compatible ferroelectric field effect transistors (FeFET) with sub 10 nm gate insulators for the first time

Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling

Abstract: We propose a novel highly scalable source-drain-junction-free field-effect transistor that we call the bulk planar junctionless transistor (BPJLT). This builds upon the idea of an isolated ultrathin highly doped device layer of which volume is fully depleted in the off-state and is around flatband in the on-state. Here, the leakage current depends on the effective device layer thickness, and we show that with well doping and/or well bias, this can be controllably made less than the physical device layer thickness in a bulk planar junction-isolated structure. We demonstrate by extensive device simulations that these additional knobs for controlling short-channel effects reduce the off-state leakage current by orders of magnitude for similar on-state currents, making the BPJLT highly scalable.

SiC power devices — Present status, applications and future perspective

Abstract: Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. Recently Schottky diodes are offered by both USA and Europe based companies. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now available on the commercial market. The interest is rapidly growing for these devices in high power and high temperature applications. The main advantages of wide bandgap semiconductors are their very high critical electric field capability. From a power device perspective the high critical field strength can be used to design switching devices with much lower losses than conventional silicon based devices both for on-state losses and reduced switching losses. This paper reviews the current state of the art in active switching device performance for both SiC and GaN. SiC material quality and epitaxy processes have greatly improved and degradation free 100 mm wafers are readily available. The SiC wafer roadmap looks very favorable as volume production takes off. For GaN materials the main application area is geared towards the lower power rating level up to 1 kV on mostly lateral FET designs. Power module demonstrations are beginning to appear in scientific reports and real applications. A short review is therefore given. Other advantages of SiC is the possibility of high temperature operation (> 300 °C) and in radiation hard environments, which could offer considerable system advantages.

Very Large Capacitance Enhancement in a Two-Dimensional Electron System

Abstract: Increases in the gate capacitance of field-effect transistor structures allow the production of lower-power devices that are compatible with higher clock rates, driving the race for developing high-κ dielectrics. However, many-body effects in an electronic system can also enhance capacitance. Onto the electron system that forms at the LaAlO 3 /SrTiO 3 interface, we fabricated top-gate electrodes that can fully deplete the interface of all mobile electrons. Near depletion, we found a greater than 40% enhancement of the gate capacitance. Using an electric-field penetration measurement method, we show that this capacitance originates from a negative compressibility of the interface electron system. Capacitance enhancement exists at room temperature and arises at low electron densities, in which disorder is strong and the in-plane conductance is much smaller than the quantum conductance.

High mobility organic thin film transistor and efficient photovoltaic devices using versatile donor–acceptor polymer semiconductor by molecular design

Abstract: In this work, we report a novel donor–acceptor based solution processable low band gap polymer semiconductor, PDPP–TNT, synthesized via Suzuki coupling using condensed diketopyrrolopyrrole (DPP) as an acceptor moiety with a fused naphthalene donor building block in the polymer backbone. This polymer exhibits p-channel charge transport characteristics when used as the active semiconductor in organic thin-film transistor (OTFT) devices. The hole mobilities of 0.65 cm2 V−1s−1 and 0.98 cm2 V−1s−1 are achieved respectively in bottom gate and dual gate OTFT devices with on/off ratios in the range of 105 to 107. Additionally, due to its appropriate HOMO (5.29 eV) energy level and optimum optical band gap (1.50 eV), PDPP–TNT is a promising candidate for organic photovoltaic (OPV) applications. When this polymer semiconductor is used as a donor and PC71BM as an acceptor in OPV devices, high power conversion efficiencies (PCE) of 4.7% are obtained. Such high mobility values in OTFTs and high PCE in OPV make PDPP–TNT a very promising polymer semiconductor for a wide range of applications in organic electronics.

CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$ -mV/decade Subthreshold Swing

Abstract: We present a vertical-silicon-nanowire-based p-type tunneling field-effect transistor (TFET) using CMOS-compatible process flow. Following our recently reported n-TFET , a low-temperature dopant segregation technique was employed on the source side to achieve steep dopant gradient, leading to excellent tunneling performance. The fabricated p-TFET devices demonstrate a subthreshold swing (SS) of 30 mV/decade averaged over a decade of drain current and an Ion/Ioff ratio of >; 105. Moreover, an SS of 50 mV/decade is maintained for three orders of drain current. This demonstration completes the complementary pair of TFETs to implement CMOS-like circuits.

Channel Length Scaling in Graphene Field-Effect Transistors Studied with Pulsed Current—Voltage Measurements

Abstract: We investigate current saturation at short channel lengths in graphene field-effect transistors (GFETs). Saturation is necessary to achieve low-output conductance required for device power gain. Dual-channel pulsed current−voltage measurements are performed to eliminate the significant effects of trapped charge in the gate dielectric, a problem common to all oxide-based dielectric films on graphene. With pulsed measurements, graphene transistors with channel lengths as small as 130 nm achieve output conductance as low as 0.3 mS/μm in saturation. The transconductance of the devices is independent of channel length, consistent with a velocity saturation model of high-field transport. Saturation velocities have a density dependence consistent with diffusive transport limited by optical phonon emission.

Terahertz responsivity of field effect transistors versus their static channel conductivity and loading effects

Abstract: We study the broadband photovoltaic response of field effect transistors on terahertz radiation. A simple physical analytical model of the response is developed. It is based on plasma density perturbation in the transistor channel by the incoming terahertz radiation. The model shows how the non-resonant detection signal is related to static (dc) transistor characteristics. We analyze loading effects related to capacitive, inductive, and resistive coupling of the detector to the read-out circuit as a function of modulation frequencies and loading resistors. As we show, the proposed physical model completed by loading effects fully describes the experimental results on the non-resonant sub-terahertz detection by all studied III-V (GaAs, GaN) and silicon based transistors. Field effect transistors were recently proposed as the best terahertz detecting pixels for fabrication of low cost focal plane arrays for terahertz imaging. This article gives prospects for electrical simulation of these transistors and their optimal integration in the focal plane arrays.

Insulating Behavior in Ultrathin Bismuth Selenide Field Effect Transistors

Abstract: Ultrathin (approximately three quintuple layer) field-effect transistors (FETs) of topological insulator Bi(2)Se(3) are prepared by mechanical exfoliation on 300 nm SiO(2)/Si susbtrates. Temperature- and gate-voltage-dependent conductance measurements show that ultrathin Bi(2)Se(3) FETs are n-type and have a clear OFF state at negative gate voltage, with activated temperature-dependent conductance and energy barriers up to 250 meV.

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

Abstract: In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.