scispace - formally typeset
Search or ask a question

Showing papers on "Field-effect transistor published in 2012"


Journal ArticleDOI
09 Jan 2012-Small
TL;DR: Although the single-layer MoS(2) device shows a rapid response after exposure to NO, the current was found to be unstable, and these FET devices can be used as gas sensors to detect nitrous oxide.
Abstract: Single- and multilayer MoS(2) films are deposited onto Si/SiO(2) using the mechanical exfoliation technique. The films were then used for the fabrication of field-effect transistors (FETs). These FET devices can be used as gas sensors to detect nitrous oxide (NO). Although the single-layer MoS(2) device shows a rapid response after exposure to NO, the current was found to be unstable. The two-, three-, and four-layer MoS(2) devices show both stable and sensitive responses to NO down to a concentration of 0.8 ppm.

1,396 citations


Journal ArticleDOI
23 May 2012-ACS Nano
TL;DR: Uniform encapsulation of MoS(2) transistor structures with silicon nitride grown by plasma-enhanced chemical vapor deposition is effective in minimizing the hysteresis, while the device mobility is improved by over 1 order of magnitude.
Abstract: Field effect transistors using ultrathin molybdenum disulfide (MoS2) have recently been experimentally demonstrated, which show promising potential for advanced electronics. However, large variations like hysteresis, presumably due to extrinsic/environmental effects, are often observed in MoS2 devices measured under ambient environment. Here, we report the origin of their hysteretic and transient behaviors and suggest that hysteresis of MoS2 field effect transistors is largely due to absorption of moisture on the surface and intensified by high photosensitivity of MoS2. Uniform encapsulation of MoS2 transistor structures with silicon nitride grown by plasma-enhanced chemical vapor deposition is effective in minimizing the hysteresis, while the device mobility is improved by over 1 order of magnitude.

951 citations


Journal ArticleDOI
TL;DR: This work presents atomic-scale images and electronic characteristics of these atomically precise devices and the impact of strong vertical and lateral confinement on electron transport and discusses the opportunities ahead for atomic- scale quantum computing architectures.
Abstract: The ability to control matter at the atomic scale and build devices with atomic precision is central to nanotechnology. The scanning tunnelling microscope can manipulate individual atoms and molecules on surfaces, but the manipulation of silicon to make atomic-scale logic circuits has been hampered by the covalent nature of its bonds. Resist-based strategies have allowed the formation of atomic-scale structures on silicon surfaces, but the fabrication of working devices-such as transistors with extremely short gate lengths, spin-based quantum computers and solitary dopant optoelectronic devices-requires the ability to position individual atoms in a silicon crystal with atomic precision. Here, we use a combination of scanning tunnelling microscopy and hydrogen-resist lithography to demonstrate a single-atom transistor in which an individual phosphorus dopant atom has been deterministically placed within an epitaxial silicon device architecture with a spatial accuracy of one lattice site. The transistor operates at liquid helium temperatures, and millikelvin electron transport measurements confirm the presence of discrete quantum levels in the energy spectrum of the phosphorus atom. We find a charging energy that is close to the bulk value, previously only observed by optical spectroscopy.

821 citations


Journal ArticleDOI
TL;DR: The fabrication of an electric double layer transistor (EDLT, a FET gated by ionic liquids) using a thin flake of MoS(2), a member of the transition metal dichalcogenides, an archetypal layered material unambiguously displayed ambipolar operation.
Abstract: Field effect transistors (FETs) made of thin flake single crystals isolated from layered materials have attracted growing interest since the success of graphene. Here, we report the fabrication of an electric double layer transistor (EDLT, a FET gated by ionic liquids) using a thin flake of MoS(2), a member of the transition metal dichalcogenides, an archetypal layered material. The EDLT of the thin flake MoS(2) unambiguously displayed ambipolar operation, in contrast to its commonly known bulk property as an n-type semiconductor. High-performance transistor operation characterized by a large "ON" state conductivity in the order of ~mS and a high on/off ratio >10(2) was realized for both hole and electron transport. Hall effect measurements revealed mobility of 44 and 86 cm(2) V(-1) s(-1) for electron and hole, respectively. The hole mobility is twice the value of the electron mobility, and the density of accumulated carrier reached 1 × 10(14) cm(-2), which is 1 order of magnitude larger than conventional FETs with solid dielectrics. The high-density carriers of both holes and electrons can create metallic transport in the MoS(2) channel. The present result is not only important for device applications with new functionalities, but the method itself would also act as a protocol to study this class of material for a broader scope of possibilities in accessing their unexplored properties.

776 citations


Journal ArticleDOI
12 Sep 2012-ACS Nano
TL;DR: The performance limit of short channel MoS(2) transistors is dominated by the large contact resistance from the Schottky barrier between Ni and MoS (2) interface, where a fully transparent contact is needed to achieve a high-performance short channel device.
Abstract: In this article, we investigate electrical transport properties in ultrathin body (UTB) MoS2 two-dimensional (2D) crystals with channel lengths ranging from 2 μm down to 50 nm. We compare the short channel behavior of sets of MOSFETs with various channel thickness, and reveal the superior immunity to short channel effects of MoS2 transistors. We observe no obvious short channel effects on the device with 100 nm channel length (Lch) fabricated on a 5 nm thick MoS2 2D crystal even when using 300 nm thick SiO2 as gate dielectric, and has a current on/off ratio up to ∼109. We also observe the on-current saturation at short channel devices with continuous scaling due to the carrier velocity saturation. Also, we reveal the performance limit of short channel MoS2 transistors is dominated by the large contact resistance from the Schottky barrier between Ni and MoS2 interface, where a fully transparent contact is needed to achieve a high-performance short channel device.

731 citations


Journal ArticleDOI
TL;DR: In this paper, the authors present low temperature electrical transport experiments in five field effect transistor devices consisting of monolayer, bilayer and trilayer MoS2 films, mechanically exfoliated onto Si/SiO2 substrate.
Abstract: We present low temperature electrical transport experiments in five field effect transistor devices consisting of monolayer, bilayer and trilayer MoS2 films, mechanically exfoliated onto Si/SiO2 substrate. Our experiments reveal that the electronic states in all films are localized well up to the room temperature over the experimentally accessible range of gate voltage. This manifests in two dimensional (2D) variable range hopping (VRH) at high temperatures, while below \sim 30 K the conductivity displays oscillatory structures in gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T0) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges in the substrate are the dominant source of disorder in MoS2 field effect devices, which leads to carrier localization as well.

638 citations


Journal ArticleDOI
TL;DR: In this paper, the authors fabricate MoS2 field effect transistors on both SiO2 and polymethyl methacrylate (PMMA) dielectrics and measure charge carrier mobility in a four-probe configuration.
Abstract: We fabricate MoS2 field effect transistors on both SiO2 and polymethyl methacrylate (PMMA) dielectrics and measure charge carrier mobility in a four-probe configuration. For multilayer MoS2 on SiO2, the mobility is 30-60 cm2/Vs, relatively independent of thickness (15-90 nm), and most devices exhibit unipolar n-type behavior. In contrast, multilayer MoS2 on PMMA shows mobility increasing with thickness, up to 470 cm2/Vs (electrons) and 480 cm2/Vs (holes) at thickness ~50 nm. The dependence of the mobility on thickness points to a long-range dielectric effect of the bulk MoS2 in increasing mobility.

613 citations


Journal ArticleDOI
TL;DR: In this article, the performance and environmental effects on back-gated bi-layer MoS2 field effect transistors were investigated and it was shown that vacuum annealing can effectively remove the absorbates and reversibly recover the device performances.
Abstract: Two-dimensional transition-metal dichalcogenides such as MoS2 are promising channel materials for transistor scaling. Here, we report the performance and environmental effects on back-gated bi-layer MoS2field-effect transistors. The devices exhibit Ohmic contacts with titanium at room temperature, on/off ratio higher than 107, and current saturation. Furthermore, we show that the devices are sensitive to oxygen and water in the ambient. Exposure to ambient dramatically reduces the on-state current by up to 2 orders of magnitude likely due to additional scattering centers from chemisorption on the defect sites of MoS2. We demonstrate that vacuum annealing can effectively remove the absorbates and reversibly recover the device performances. This method significantly reduces the large variations in MoS2 device caused by extrinsic factors.

545 citations


Journal ArticleDOI
TL;DR: In this paper, the authors report the fabrication of back-gated field effect transistors (FETs) using ultra-thin, mechanically exfoliated MoSe2 flakes.
Abstract: We report the fabrication of back-gated field-effect transistors (FETs) using ultra-thin, mechanically exfoliated MoSe2 flakes. The MoSe2 FETs are n-type and possess a high gate modulation, with On/Off ratios larger than 106. The devices show asymmetric characteristics upon swapping the source and drain, a finding explained by the presence of Schottky barriers at the metal contact/MoSe2 interface. Using four-point, back-gated devices, we measure the intrinsic conductivity and mobility of MoSe2 as a function of gate bias, and temperature. Samples with a room temperature mobility of ∼ 50 cm2/V·s show a strong temperature dependence, suggesting phonons are a dominant scattering mechanism.

470 citations


Journal ArticleDOI
TL;DR: In this article, the authors report the fabrication of back-gated field effect transistors (FETs) using ultra-thin, mechanically exfoliated MoSe2 flakes.
Abstract: We report the fabrication of back-gated field-effect transistors (FETs) using ultra-thin, mechanically exfoliated MoSe2 flakes. The MoSe2 FETs are n-type and possess a high gate modulation, with On/Off ratios larger than 106. The devices show asymmetric characteristics upon swapping the source and drain, a finding explained by the presence of Schottky barriers at the metal contact/MoSe2 interface. Using four-point, back-gated devices we measure the intrinsic conductivity and mobility of MoSe2 as a function of gate bias, and temperature. Samples with a room temperature mobility of ~50 cm2/V.s show a strong temperature dependence, suggesting phonons are a dominant scattering mechanism.

457 citations


Journal ArticleDOI
TL;DR: Simulations show that the bandwidth of this branched intracellular nanotube FET (BIT-FET) is high enough for it to record fast action potentials even when the nanot tube diameter is decreased to 3 nm, a length scale which is well below that accessible with other methods.
Abstract: A silicon nanowire field-effect transistor coupled to the interior of a cell by means of a hollow silicon dioxide nanotube can detect changes in the electric potential of the intracellular fluid.

Book
25 Nov 2012
TL;DR: In this paper, the Schottky-Mott theory of ideal metal-Semiconductor contact has been applied to metal-semiconductor interfaces, and a number of interesting results have been reported.
Abstract: 1. Physics of Schottky Barrier Junctions.- 1. Introduction.- 2. Origins of Barrier Height.- 2.1. Schottky-Mott Theory of Ideal Metal-Semiconductor Contact.- 2.2. Modifications to Schottky Theory.- 2.3. Classifications of Metal-Semiconductor Interfaces.- 2.4. Contacts on Reactive Interfaces.- 2.5. Contacts with Surface States and an Insulating Interfacial Layer.- 2.6. Contacts on Vacuum Cleaved Surfaces.- 3. Measurement of Barrier Height.- 3.1. Capacitance-Voltage Measurement.- 3.2. Current-Voltage Measurement.- 3.3. Photoelectric Measurement.- 4. Results of Barrier Height Measurements.- 4.1. Chemically Prepared Surfaces.- 4.2. Vacuum Cleaved Surfaces.- 4.3. Concluding Remarks.- 5. Capacitance-Voltage Characteristics.- 5.1. Electric Field and Potential Distribution in the Depletion Region.- 5.2. Depletion Region Capacitance.- 5.2.1. Ideal Schottky Barrier.- 5.2.2. Effect of Minority Carriers.- 5.2.3. Effect of Interfacial Layer.- 5.2.4. Effect of Deep Traps.- 6. Current-Voltage Characteristics.- 6.1. Transport Mechanisms.- 6.1.1. Diffusion and Thermionic Emission over the Barrier.- 6.1.2. Tunneling through the Barrier.- 6.1.3. Carrier Generation and Recombination in the Junction Depletion Region.- 6.1.4. Minority Carrier Injection.- 6.2. Forward Characteristics.- 6.3. Reverse Characteristics.- 7. Transient Behavior.- 8. Low-Resistance Schottky Barrier Contacts.- References.- 2. Interface Chemistry and Structure of Schottky Barrier Formation.- 1. Introduction.- 2. Perspectives on Schottky Barrier Formation.- 2.1. Introduction.- 2.2. Brief Review of Phenomenological Schottky Barrier Data.- 3. The Chemistry and Structure of the Interfacial Layer.- 3.1. Synopsis of the Layer-by-Layer Evolution.- 3.2. Some Techniques for Studying the Stages of Interface Formation.- 4. Evolution of the Interfacial Layer.- 4.1. Stage 0: The Clean Semiconductor Surface.- 4.1.1. Silicon (100) and (111) Surfaces.- 4.1.2. GaAs (110) and GaAs (100) Surfaces.- 4.2. Stage 1: The Dilute Limit (< 1/2 Monolayer).- 4.3. Stage 2: Monolayer Formation-Metal Film Nucleation.- 4.4. Stage 3: Additional Monolayers and Interdiffusion.- 4.5. Some Specific Characteristics of the Interfacial Layers.- 5. Formation of Interface States.- 5.1. Intrinsic Interface States Derived from the Metal and Semiconductor.- 5.2. Localized Defect and Impurity Related States.- 5.3. Interface States and the Stages of Interface Formation.- 6. Case Studies of the Chemistry and Structure of Schottky Barrier Formation.- 6.1. Case Studies of Silicon Schottky Barriers.- 6.1.1. Al, Ag, Cu, and Au Schottky Barriers.- 6.1.2. Silicide-Silicon Interfaces.- 6.2. Case Studies of III-V and II-VI Compound Semiconductor Schottky Barriers.- 6.2.1. The Ga-Al-As System.- 6.2.2. The GaAlAs Ternary System with Au Schottky Barriers.- 6.2.3. InP.- 6.2.4. Some II-VI Examples.- 7. Summary.- References.- 3. Fabrication and Characterization of Metal-Semiconductor Schottky Barrier Junctions.- 1. Introduction.- 2. Selection of Semiconductor Materials.- 3. Metal-Semiconductor Systems.- 3.1. Metal-Silicon Systems.- 3.2. Metal-GaAs Systems.- 3.3. Multilayer Metallization Systems.- 4. Design Considerations.- 5. Fabrication Technology.- 5.1. Surface Processing.- 5.2. Dielectric Film Deposition.- 5.3. Ohmic Contact Formation.- 5.4. Metal Deposition.- 5.5. Other Steps.- 6. Characterization.- References.- 4. Schottky-Barrier-Type Optoelectronic Structures.- 1. Introduction.- 2. Barrier Formation in Schottky-Barrier-Type Junctions.- 3. Transport in Schottky-Barrier-Type Structures.- 3.1. MS and MIS Structures.- 3.2. SIS Structures.- 4. Schottky-Barrier-Type Optoelectronic Structures.- 4.1. Schottky-Barrier-Type Light-Emitting Structures.- 4.2. Schottky-Barrier-Type Photodiodes.- 4.3. Schottky-Barrier-Type Photovoltaic Devices.- 4.3.1. MS and MIS Photovoltaic Devices.- 4.3.2. SIS Photovoltaic Devices.- 3. Summary.- References.- 5. Schottky Barrier Photodiodes.- 1. Introduction.- 2. General Parameters of Photodiodes.- 2.1. Signal-to-Noise Ratio (S/N).- 2.2. Noise Equivalent Power (NEP).- 2.3. Detectivity (D).- 2.4. Normalized Detectivity (D*).- 2.5. Detectivity Normalized Also with Respect to the Field of View(D**).- 2.6. Resistance Area Product.- 2.7. Response Time.- 3. Selection of Materials.- 3.1. Metal Systems.- 3.2. Semiconducting Materials.- 4. Fabrication Technology.- 5. Techniques for Evaluating Device Parameters.- 5.1. Current-Voltage Characteristics.- 5.2. Capacitance-Voltage Characteristics.- 5.3. Photoelectric Measurements.- 5.4. Electron Beam Induced Current Technique.- 6. Applications.- 7. Conclusions.- References.- 6. Microwave Schottky Barrier Diodes.- 1. Introduction.- 2. Diode Design Considerations.- 2.1. Equivalent Circuit.- 2.2. Frequency Conversion.- 2.3. Basic Mixer Diode RF Parameters.- 2.3.1. Conversion Loss Theory.- 2.3.2. Noise-Temperature Ratio.- 2.3.3. Overall Receiver Noise Figure.- 2.3.4. Mixer Noise Temperature.- 2.3.5. RF Impedance.- 2.3.6. IF Impedance.- 2.3.7. Receiver Sensitivity.- 2.3.8. Doppler Shift.- 2.3.9. Typical Doppler Radar System.- 2.4. Basic Detector RF Parameters.- 2.4.1. Video Resistance (Rv).- 2.4.2. Voltage Sensitivity.- 2.4.3. Current Sensitivity ?.- 2.4.4. Minimum Detectable Signal (MDS).- 2.4.5. Tangential Signal Sensitivity (TSS).- 2.4.6. Nominal Detectable Signal (NDS).- 2.4.7. Noise Equivalent Power (NEP).- 2.4.8. Video Bandwidth.- 2.4.9. Superheterodyne vs. Single Detection.- 2.5. Mixer Configurations.- 2.5.1. Single-Ended Mixer.- 2.5.2. Single-Balanced Mixer.- 2.5.3. Double-Balanced Mixer.- 2.5.4. Image Rejection Mixer.- 2.5.5. Image Enhanced or Image Recovery Mixer.- 3. Properties of Schottky Barrier Diodes.- 3.1. Diode Theory.- 3.2. DC Parameters.- 3.2.1. Junction Capacitance.- 3.2.2. Overlay Capacitance.- 3.2.3. Series Resistance.- 3.2.4. Figure of Merit.- 3.3. Semiconductor Materials.- 3.4. Epitaxial GaAs.- 3.5. Barrier Height Lowering.- 3.6. Fabrication.- 4. Microwave Performance.- 4.1. Mixer Diodes.- 4.2. Detector Diodes.- 5. RF Pulse and CW Burnout.- 5.1. Introduction.- 5.2. Factors Affecting RF Burnout.- 5.3. Experimental Results.- 5.4. Physical Analysis of RF Pulsed Silicon Schottky Barrier Failed Diodes.- 5.5. Physical Analysis of RF Pulsed Millimeter GaAs Schottky Barrier Failed Diodes.- 5.6. Electrostatic Failure of Silicon Schottky Barrier Diodes.- 6. Conclusions.- References.- 7. Metal-Semiconductor Field Effect Transistors.- 1. Introduction.- 2. Small-Signal FET Theory.- 3. Design Parameters of a Low-Noise Device.- 4. Practical Small-Signal FET Fabrication Techniques.- 4.1. Material Growth Techniques.- 4.2. FET Fabrication Technology.- 5. GaAs Power Field Effect Transistors.- 5.1. Principle of Power FET Operation.- 5.2. Thermal Impedance.- 5.3. Power FET Technology.- 6. Conclusions.- References.- 8. Schottky Barrier Gate Charge-Coupled Devices.- 1. Introduction.- 2. Schottky Gate CCDs.- 3. Potential-Charge Relationships.- 3.1. Surface Channel CCD.- 3.2. Bulk Channel CCD.- 3.3. Schottky Gate CCD.- 4. Charge Storage Capacity.- 4.1. Surface Channel CCD.- 4.2. Bulk Channel CCD.- 4.3. Schottky Gate CCD.- 5. Charge Transfer.- 5.1. Charge Transfer Efficiency.- 5.2. Charge Transfer Mechanisms.- 5.2.1. Surface Channel CCD.- 5.2.2. Bulk Channel CCD.- 5.2.3. Schottky Gate CCD.- 6. Input-Output Circuits.- 7. Schottky Gate Heterojunction CCDs.- 8. Experimental Results.- 8.1. High-Frequency Devices.- 8.2. Heterojunction Devices.- 9. Applications.- References.- 9. Schottky Barriers on Amorphous Si and their Applications.- 1. Introduction.- 2. Properties of Amorphous Si.- 2.1. Deposition Methods.- 2.2. Structural Properties.- 2.3. Electronic Properties.- 2.4. Surfaces.- 3. The Schottky Barrier on ?-Si:H.- 3.1. Current-Voltage Measurements.- 3.2. Capacitance Measurements.- 3.3 Internal Photoemission.- 4. Interface Kinetics and Its Effect on the Schottky Barrier.- 5. Applications.- 5.1. Drift Mobility.- 5.2. Deep Level Transient Spectroscopy.- 5.3. Solar Cells.- 5.4. Thin Film Transistors.- 6. Concluding Remarks.- References.

Journal ArticleDOI
TL;DR: A comprehensive overview on the subject of current injection in organic thin film transistors is offered: physical principles concerning energy level (mis)alignment at interfaces, models describing charge injection, technologies for interface tuning, and techniques for characterizing devices.
Abstract: A high-mobility organic semiconductor employed as the active material in a field-effect transistor does not guarantee per se that expectations of high performance are fulfilled. This is even truer if a downscaled, short channel is adopted. Only if contacts are able to provide the device with as much charge as it needs, with a negligible voltage drop across them, then high expectations can turn into high performances. It is a fact that this is not always the case in the field of organic electronics. In this review, we aim to offer a comprehensive overview on the subject of current injection in organic thin film transistors: physical principles concerning energy level (mis)alignment at interfaces, models describing charge injection, technologies for interface tuning, and techniques for characterizing devices. Finally, a survey of the most recent accomplishments in the field is given. Principles are described in general, but the technologies and survey emphasis is on solution processed transistors, because it is our opinion that scalable, roll-to-roll printing processing is one, if not the brightest, possible scenario for the future of organic electronics. With the exception of electrolyte-gated organic transistors, where impressively low width normalized resistances were reported (in the range of 10 Ω·cm), to date the lowest values reported for devices where the semiconductor is solution-processed and where the most common architectures are adopted, are ∼10 kΩ·cm for transistors with a field effect mobility in the 0.1-1 cm(2)/Vs range. Although these values represent the best case, they still pose a severe limitation for downscaling the channel lengths below a few micrometers, necessary for increasing the device switching speed. Moreover, techniques to lower contact resistances have been often developed on a case-by-case basis, depending on the materials, architecture and processing techniques. The lack of a standard strategy has hampered the progress of the field for a long time. Only recently, as the understanding of the rather complex physical processes at the metal/semiconductor interfaces has improved, more general approaches, with a validity that extends to several materials, are being proposed and successfully tested in the literature. Only a combined scientific and technological effort, on the one side to fully understand contact phenomena and on the other to completely master the tailoring of interfaces, will enable the development of advanced organic electronics applications and their widespread adoption in low-cost, large-area printed circuits.

Journal ArticleDOI
TL;DR: The OFETs and complementary-like inverters are among the best reported organic devices to date, in terms of mobility, voltage gain, symmetry, p-and n-type channel balance, low operating voltage window and high ON/OFF ratio as discussed by the authors.
Abstract: strong intermolecular interactions and with reversible reduction and oxidation reactions characterized by means of optical, electrical, and morphological investigations on thin indigo fi lms. The OFETs and complementary-like inverters are among the best reported organic devices to date, in terms of mobility, voltage gain, symmetry, p- and n-type channel balance, low operating voltage window and high ON/OFF ratio. Moreover, these devices show that high performance electronics can be fabricated entirely from non-toxic, biodegradable, and extremely cheap materials.

Journal ArticleDOI
TL;DR: This novel nanotransistor technology makes way for a simple and compact hardware platform that can be flexibly reconfigured during operation to perform different logic computations yielding unprecedented circuit design flexibility.
Abstract: Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce s...

Patent
Jhon-Jhy Liaw1
30 Nov 2012
TL;DR: In this paper, a dielectric layer is formed over a portion of an SRAM cell and a contact plug is formed in the contact opening, where a first mask layer and a second mask layer are formed over the dielectrics layer and patterned.
Abstract: A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening.

PatentDOI
TL;DR: In this paper, a field effect transistor (FET) with a source electrode and a drain electrode distanced apart from each other on a semi-conductor substrate, and a gate electrode consisting of a uniform layer of reduced graphene oxide encapsulated semiconductor nanoparticles (rGO-NPs), wherein the gate electrode is disposed between and contacts both the source and drain electrodes.
Abstract: A field effect transistor (FET) with a source electrode and a drain electrode distanced apart from each other on a semi-conductor substrate, and a gate electrode consisting of a uniform layer of reduced graphene oxide encapsulated semiconductor nanoparticles (rGO-NPs), wherein the gate electrode is disposed between and contacts both the source and drain electrodes. Methods of making and assay methods using the FETs are also disclosed, including methods in which the rGO-NPs are functionalized with binding partners for biomarkers.

Journal ArticleDOI
TL;DR: This study of electro-mechanical properties suggests that solution-processable organic semiconductors are suitable for applications in flexible electronics, provided that integration with other important technological advances, such as device scalability and low-voltage operation, is achieved in the future.
Abstract: Organic electronic materials are promising candidates for applications in which flexible electronic devices are required. Yi et al. demonstrate a high-performance, flexible organic transistor based on solution-processed small molecules that can be fabricated with a simple, low-cost process.

Journal ArticleDOI
TL;DR: A quantitative analysis of results on different p-channel transistors indicate the importance of the semiconductor molecular polarizability and the structure of the charge transport layers in the crystal for the observation of band-like transport in OFETs.
Abstract: The Hall effect and an increase of field-effect mobility with decreasing temperature is observed in n-channel single-crystal organic field-effect transistors (OFETs). A quantitative analysis of these findings, together with results on different p-channel transistors, indicate the importance of the semiconductor molecular polarizability and the structure of the charge transport layers in the crystal for the observation of band-like transport in OFETs

Journal ArticleDOI
TL;DR: Electrolyte-Gated OFET (EGOFET) architecture, where EGOFETs differ from OFETs, as in OECTs, in that the gate is separated from the semiconductor by an electrolyte, which allows low voltage operation compared with OfETs gated via solid dielectrics.
Abstract: Organic electronics have, over the past two decades, developed into an exciting area of research and technology to replace classic inorganic semiconductors. Organic photovoltaics, light-emitting diodes, and thin-film transistors are already well developed and are currently being commercialized for a variety of applications. More recently, organic transistors have found new applications in the field of biosensors. The progress made in this direction is the topic of this review. Various configurations are presented, with their detection principle, and illustrated by examples from the literature.

Journal ArticleDOI
TL;DR: A flexible glucose sensor using a CVD-grown graphene-based field-effect-transistor (FET) is demonstrated, which provides excellent fitting to a model curve even when deformed, high resolution, and continuous real-time monitoring.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, two independent gate-all-around electrodes and vertically stacked SiNW channels are used to enable dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device.
Abstract: We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I on /I off > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.

Journal ArticleDOI
TL;DR: In this article, the authors reported the realization of field effect transistors (FETs) made with chemically synthesized multilayer crystal semiconductor WS2, which demonstrated ambipolar behavior and a high (∼105×) on/off current ratio at room temperature with current saturation.
Abstract: We report the realization of field-effect transistors (FETs) made with chemically synthesized multilayer crystal semiconductor WS2. The Schottky-barrier FETs demonstrate ambipolar behavior and a high (∼105×) on/off current ratio at room temperature with current saturation. The behavior is attributed to the presence of an energy bandgap in the ultrathin layered semiconductor crystal material. The FETs also show clear photo response to visible light. The promising electronic and optical characteristics of the devices combined with the chemical synthesis, and flexibility of layered semiconductor crystals such as WS2 make them attractive for future electronic and optical devices.

Journal ArticleDOI
TL;DR: Ultrahigh-mobility organic field-effect transistors (OFETs) based on a CDT-BTZ donor-acceptor copolymer are realized by reaching high molecular order and pronounced alignment in single fibers within a short OFET channel via solution processing.
Abstract: Ultrahigh-mobility organic field-effect transistors (OFETs) based on a CDT-BTZ donor-acceptor copolymer are realized by reaching high molecular order and pronounced alignment in single fibers within a short OFET channel via solution processing. The macromolecules directionally self-assemble in a quasi crystal-like order in the fibers providing in this way an unhindered charge carrier pathway with mobilities as high as 5.5 cm(2) V(-1) s(-1).

Journal ArticleDOI
09 Jan 2012-Small
TL;DR: Bottom-gate, top-contact organic thin-film transistors with excellent static characteristics and fast unipolar ring oscillators with significant contribution of the transfer length to the relation between channel length, contact length, Contact resistance, effective mobility, and cutoff frequency are fabricated.
Abstract: Keywords: organic thin-film transistors ; contact length ; contact resistance ; cutoff frequency ; Thin-Film Transistors ; Field-Effect Transistors ; Artificial Skin ; Performance ; Fabrication ; Dielectrics ; Matrix Reference EPFL-ARTICLE-175161doi:10.1002/smll.201101677View record in Web of Science Record created on 2012-02-23, modified on 2017-05-12

Journal ArticleDOI
TL;DR: Phosphorus-doped double-layered graphene field-effect transistors (PDGFETs) show much stronger air-stable n-type behavior than nitrogen-doping double-Layered graphene FETs, even under an oxygen atmosphere, due to strong nucleophilicity, which may lead to real applications for air- stable n- type graphene channels.
Abstract: Phosphorus-doped double-layered graphene field-effect transistors (PDGFETs) show much stronger air-stable n-type behavior than nitrogen-doped double-layered graphene FETs (NDGFETs), even under an oxygen atmosphere, due to strong nucleophilicity, which may lead to real applications for air-stable n-type graphene channels.

Journal ArticleDOI
TL;DR: Enhanced sensing of biological species by optimization of operating parameters and fundamental understanding for SiNW FET detection limit was obtained.
Abstract: Silicon nanowire (SiNW) field effect transistors (FETs) have emerged as powerful sensors for ultrasensitive, direct electrical readout, and label-free biological/chemical detection. The sensing mechanism of SiNW-FET can be understood in terms of the change in charge density at the SiNW surface after hybridization. So far, there have been limited systematic studies on fundamental factors related to device sensitivity to further make clear the overall effect on sensing sensitivity. Here, we present an analytical result for our triangle cross-section wire for predicting the sensitivity of nanowire surface-charge sensors. It was confirmed through sensing experiments that the back-gated SiNW-FET sensor had the highest percentage current response in the subthreshold regime and the sensor performance could be optimized in low buffer ionic strength and at moderate probe concentration. The optimized SiNW-FET nanosensor revealed ultrahigh sensitivity for rapid and reliable detection of target DNA with a detection limit of 0.1 fM and high specificity for single-nucleotide polymorphism discrimination. In our work, enhanced sensing of biological species by optimization of operating parameters and fundamental understanding for SiNW FET detection limit was obtained.

Journal ArticleDOI
TL;DR: Graphene, a one-atom-thick two-dimensional carbon sheet, has been extensively studied owing to its broad applications in nanoelectronics, but the application of graphene in FETs is limited because of its semi-metallic behavior with zero bandgap.
Abstract: Graphene, a one-atom-thick two-dimensional carbon sheet, has been extensively studied owing to its broad applications in nanoelectronics, [ 1 , 2 ] nanocomposites, [ 3 , 4 ] chemical sensors and biosensors, [ 5–10 ] solar cells, [ 11–13 ] and electrical and optical devices. [ 14–16 ] However, the application of graphene in fi eldeffect transistors (FETs) is limited because of its semi-metallic behavior with zero bandgap. [ 17 , 18 ] Cutting graphene sheets into nanoribbons led to bandgap opening, with current ON/OFF ratio large enough for transistor operation. [ 19–23 ] Unfortunately, FET devices based on the individual nanoribbons exhibited low driving current and conductance. [ 22 ]

Journal ArticleDOI
TL;DR: In this paper, a field effect transistor-based terahertz detector for the operation at discrete frequencies spanning from 0.2 to 4.3 THz is presented.
Abstract: This paper reports on field-effect-transistor-based terahertz detectors for the operation at discrete frequencies spanning from 0.2 to 4.3 THz. They are implemented using a 150-nm CMOS process technology, employ self-mixing in the n-channels of the transistors and operate well above the transistors' cutoff frequency. The theoretical description of device operation by Dyakonov and Shur is extended in order to describe the device impedance, responsivity, and noise-equivalent power for a novel detection concept, which couples the signal to the drain. This approach enables quasi-static (QS) detection and calibration of the detectors. The different transport regimes (i.e., QS, distributed resistive, and plasmonic mixing) and their transitions are theoretically discussed and experimentally accessed. Responsivity values of 350 V/W at 595 GHz, 30 V/W at 2.9 THz, and 5 V/W at 4.1 THz are reported. At 0.595 THz, we determine the optical noise equivalent power (NEP) to be 42 pW/√Hz ; at 2.9 THz, the value is 487 pW/√Hz. All values are reported for optimum gate bias with respect to NEP at 295 K. For 0.595 THz, theory predicts a NEP value at threshold as low as 2 pW/√Hz for ideal coupling of the radiation.

Journal ArticleDOI
TL;DR: It is demonstrated that semiconductor nanowires can also be used as building blocks for the realization of high-sensitivity terahertz detectors based on a 1D field-effect transistor configuration.
Abstract: The growth of semiconductor nanowires (NWs) has recently opened new paths to silicon integration of device families such as light-emitting diodes, high-efficiency photovoltaics, or high-responsivity photodetectors. It is also offering a wealth of new approaches for the development of a future generation of nanoelectronic devices. Here we demonstrate that semiconductor nanowires can also be used as building blocks for the realization of high-sensitivity terahertz detectors based on a 1D field-effect transistor configuration. In order to take advantage of the low effective mass and high mobilities achievable in III–V compounds, we have used InAs nanowires, grown by vapor-phase epitaxy, and properly doped with selenium to control the charge density and to optimize source–drain and contact resistance. The detection mechanism exploits the nonlinearity of the transfer characteristics: the terahertz radiation field is fed at the gate-source electrodes with wide band antennas, and the rectified signal is then rea...