Showing papers on "Field-effect transistor published in 2013"
TL;DR: This work demonstrates field-effect transistors with MoS2 channels, hBN dielectric, and graphene gate electrodes, and takes advantage of the mechanical strength and flexibility of these materials to create flexible and transparent FETs that show unchanged performance up to 1.5% strain.
Abstract: Atomically thin forms of layered materials, such as conducting graphene, insulating hexagonal boron nitride (hBN), and semiconducting molybdenum disulfide (MoS2), have generated great interests recently due to the possibility of combining diverse atomic layers by mechanical “stacking” to create novel materials and devices. In this work, we demonstrate field-effect transistors (FETs) with MoS2 channels, hBN dielectric, and graphene gate electrodes. These devices show field-effect mobilities of up to 45 cm2/Vs and operating gate voltage below 10 V, with greatly reduced hysteresis. Taking advantage of the mechanical strength and flexibility of these materials, we demonstrate integration onto a polymer substrate to create flexible and transparent FETs that show unchanged performance up to 1.5% strain. These heterostructure devices consisting of ultrathin two-dimensional (2D) materials open up a new route toward high-performance flexible and transparent electronics.
1,004 citations
TL;DR: The design and first demonstration of high-performance n-type monolayer tungsten diselenide (WSe2) field effect transistors (FET) by selecting the contact metal based on understanding the physics of contact between metal and monolayers WSe2 corroborates the superb potential of WSe 2 for complementary digital logic applications.
Abstract: This work presents a systematic study toward the design and first demonstration of high-performance n-type monolayer tungsten diselenide (WSe2) field effect transistors (FET) by selecting the contact metal based on understanding the physics of contact between metal and monolayer WSe2. Device measurements supported by ab initio density functional theory (DFT) calculations indicate that the d-orbitals of the contact metal play a key role in forming low resistance ohmic contacts with monolayer WSe2. On the basis of this understanding, indium (In) leads to small ohmic contact resistance with WSe2 and consequently, back-gated In–WSe2 FETs attained a record ON-current of 210 μA/μm, which is the highest value achieved in any monolayer transition-metal dichalcogenide- (TMD) based FET to date. An electron mobility of 142 cm2/V·s (with an ON/OFF current ratio exceeding 106) is also achieved with In–WSe2 FETs at room temperature. This is the highest electron mobility reported for any back gated monolayer TMD materia...
868 citations
TL;DR: In this paper, the authors fabricate MoS2 field effect transistors on both SiO2 and polymethyl methacrylate (PMMA) dielectrics and measure charge carrier mobility in a four-probe configuration.
Abstract: We fabricate MoS2 field effect transistors on both SiO2 and polymethyl methacrylate (PMMA) dielectrics and measure charge carrier mobility in a four-probe configuration. For multilayer MoS2 on SiO2, the mobility is 30–60 cm2/Vs, relatively independent of thickness (15–90 nm), and most devices exhibit unipolar n-type behavior. In contrast, multilayer MoS2 on PMMA shows mobility increasing with thickness, up to 470 cm2/Vs (electrons) and 480 cm2/Vs (holes) at thickness ∼50 nm. The dependence of the mobility on thickness points to a long-range dielectric effect of the bulk MoS2 in increasing mobility.
640 citations
TL;DR: In this article, single-crystal gallium oxide (Ga2O3) metal-oxide-semiconductor field effect transistors were fabricated on a semi-insulating β-Ga 2O3 (010) substrate.
Abstract: Single-crystal gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors were fabricated on a semi-insulating β-Ga2O3 (010) substrate. A Sn-doped n-Ga2O3 channel layer was grown by molecular-beam epitaxy. Si-ion implantation doping was performed to source and drain electrode regions for obtaining low-resistance ohmic contacts. An Al2O3 gate dielectric film formed by atomic layer deposition passivated the device surface and significantly reduced gate leakage. The device with a gate length of 2 μm showed effective gate modulation of the drain current with an extremely low off-state drain leakage of less than a few pA/mm, leading to a high drain current on/off ratio of over ten orders of magnitude. A three-terminal off-state breakdown voltage of 370 V was achieved. Stable transistor operation was sustained at temperatures up to 250 °C.
544 citations
TL;DR: Detailed studies of MoS2 transistors on industrial plastic sheets reveal robust electronic properties down to a bending radius of 1 mm which is comparable to previous reports for flexible graphene transistors, and provides guidance for achieving flexible MoS 2 transistors that are reliable at sub-mm bending radius.
Abstract: While there has been increasing studies of MoS2 and other two-dimensional (2D) semiconducting dichalcogenides on hard conventional substrates, experimental or analytical studies on flexible substrates has been very limited so far, even though these 2D crystals are understood to have greater prospects for flexible smart systems. In this article, we report detailed studies of MoS2 transistors on industrial plastic sheets. Transistor characteristics afford more than 100x improvement in the ON/OFF current ratio and 4x enhancement in mobility compared to previous flexible MoS2 devices. Mechanical studies reveal robust electronic properties down to a bending radius of 1 mm which is comparable to previous reports for flexible graphene transistors. Experimental investigation identifies that crack formation in the dielectric is the responsible failure mechanism demonstrating that the mechanical properties of the dielectric layer is critical for realizing flexible electronics that can accommodate high strain. Our uniaxial tensile tests have revealed that atomic-layer-deposited HfO2 and Al2O3 films have very similar crack onset strain. However, crack propagation is slower in HfO2 dielectric compared to Al2O3 dielectric, suggesting a subcritical fracture mechanism in the thin oxide films. Rigorous mechanics modeling provides guidance for achieving flexible MoS2 transistors that are reliable at sub-mm bending radius.
457 citations
TL;DR: In this article, a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept was performed using calibrated simulations.
Abstract: Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.
433 citations
TL;DR: In this paper, the authors demonstrate pronounced ambipolar device characteristics of multilayer WSe2 FETs using different contact electrodes and reveal that nickel electrodes facilitate electron injection while palladium electrodes are more efficient for hole injection.
Abstract: One of the most relevant features that a semiconducting channel material can offer when used in a field-effect transistor (FET) layout is its capability to enable both electron transport in the conduction band and hole transport in the valence band. In this way, complementary metal-oxide-semiconductor type applications become feasible once similar electron and hole drive current densities are achieved, and the threshold voltages are properly adjusted. In this article, we demonstrate pronounced ambipolar device characteristics of multilayer WSe2 FETs using different contact electrodes. Our study reveals that nickel electrodes facilitate electron injection while palladium electrodes are more efficient for hole injection. We also show, as an interesting demonstration, that by using nickel as the source contact electrode and palladium as the drain contact electrode, ambipolar device characteristics with similar on-state performance for both the electron and the hole branch can be achieved in WSe2 FETs. Finally, we discuss a unique technique based on the asymmetry in the ambipolar device characteristics to extract the Schottky barrier heights for such metal to WSe2 contacts.
366 citations
TL;DR: This review describes recent developments in the field-effect transistors (FETs) with gate dielectrics of ionic liquids, which have attracted much attention due to their wide electrochemical windows, low vapor pressures, and high chemical and physical stability.
Abstract: Charge carrier control is a key issue in the development of electronic functions of semiconductive materials. Beyond the simple enhancement of conductivity, high charge carrier accumulation can realize various phenomena, such as chemical reaction, phase transition, magnetic ordering, and superconductivity. Electric double layers (EDLs), formed at solid-electrolyte interfaces, induce extremely large electric fields. This results in a high charge carrier accumulation in the solid, much more effectively than solid dielectric materials. In the present review, we describe recent developments in the field-effect transistors (FETs) with gate dielectrics of ionic liquids, which have attracted much attention due to their wide electrochemical windows, low vapor pressures, and high chemical and physical stability. We explain the capacitance effects of ionic liquids, and describe the various combinations of ionic liquids and organic and inorganic semiconductors that are used to achieve such effects as high transistor performance, insulator-metal transitions, superconductivity, and ferromagnetism, in addition to the applications of the ionic-liquid EDL-FETs in logic devices. We discuss the factors controlling the mobility and threshold voltage in these types of FETs, and show the ionic liquid dependence of the transistor performance.
321 citations
TL;DR: In this paper, field effect transistors for logic applications, based on two representative two-dimensional (2D) materials, graphene and MoS2, are discussed, and the future developments in 2D material transistors are discussed.
Abstract: Field-effect transistors (FETs) for logic applications, based on two representative two-dimensional (2D) materials, graphene and MoS2, are discussed. These materials have drastically different properties and require different considerations. The unique band structure of graphene necessitates engineering of the Dirac point, including the opening of the bandgap, the doping and the interface, before the graphene can be used in logic applications. On the other hand, MoS2 is a semiconductor, and its electron transport depends heavily on the surface properties, the number of layers, and the carrier density. Finally, we discuss the prospects for the future developments in 2D material transistors.
319 citations
TL;DR: In this paper, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated, which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a TFET.
Abstract: In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high- $k$ dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high $I_{{\rm ON}}/I_{{\rm OFF}}$ ratio $(\sim 6\times 10^{8})$ , a point subthreshold slope (SS) of ${\sim}{\rm 38}~{\rm mV}$ /decade, and an average SS of ${\sim}{\rm 70}~{\rm mV}$ /decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.
301 citations
TL;DR: The recent progress in flexible all-carbon nanomaterial transistor research is highlighted, and this all- carbon strategy opens up a perspective to realize extremely flexible, stretchable, and transparent electronics with a relatively low-cost and fast fabrication technique, compared to traditional rigid silicon, metal and metal oxide electronics.
Abstract: Carbon nanotubes (CNTs) and graphene have attracted great attention for numerous applications for future flexible electronics, owing to their supreme properties including exceptionally high electronic conductivity and mechanical strength. Here, the progress of CNT- and graphene-based flexible thin-film transistors from material preparation, device fabrication techniques to transistor performance control is reviewed. State-of-the-art fabrication techniques of thin-film transistors are divided into three categories: solid-phase, liquid-phase, and gas-phase techniques, and possible scale-up approaches to achieve realistic production of flexible nanocarbon-based transistors are discussed. In particular, the recent progress in flexible all-carbon nanomaterial transistor research is highlighted, and this all-carbon strategy opens up a perspective to realize extremely flexible, stretchable, and transparent electronics with a relatively low-cost and fast fabrication technique, compared to traditional rigid silicon, metal and metal oxide electronics.
TL;DR: A generalized Coulomb scattering model is developed with strictly considering device configurative conditions, that is, asymmetric dielectric environments and lopsided carrier distribution, and reveals that the carrier scattering from interfacial Coulomb impurities is greatly intensified in extremely thinned channels, resulting from shortened interaction distance between impurities and carriers.
Abstract: Two-dimensional semiconductors are structurally ideal channel materials for the ultimate atomic electronics after silicon era. A long-standing puzzle is the low carrier mobility ({\mu}) in them as compared with corresponding bulk structures, which constitutes the main hurdle for realizing high-performance devices. To address this issue, we perform combined experimental and theoretical study on atomically thin MoS2 field effect transistors with varying the number of MoS2 layers (NLs). Experimentally, an intimate relation is observed with a 10-fold degradation in {\mu} for extremely thinned monolayer channels. To accurately describe the carrier scattering process and shed light on the origin of the thinning-induced mobility degradation, a generalized Coulomb scattering model is developed with strictly considering device configurative conditions, i.e., asymmetric dielectric environments and lopsided carrier distribution. We reveal that the carrier scattering from interfacial Coulomb impurities (e.g., chemical residues, gaseous adsorbates and surface dangling bonds) is greatly intensified in extremely thinned channels, resulting from shortened interaction distance between impurities and carriers. Such a pronounced factor may surpass lattice phonons and serve as dominant scatterers. This understanding offers new insight into the thickness induced scattering intensity, highlights the critical role of surface quality in electrical transport and would lead to rational performance improvement strategies for future atomic electronics.
TL;DR: The fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide, a strong candidate for next-generation atomic electronics.
Abstract: Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum disulfide (MoS2), the first recognized 2D semiconductor, it is also important to explore the wide spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high performance. Here we report the fabrication of high-performance top-gated field-effect transistors (FETs) and related logic gates from monolayer tin disulfide (SnS2), a non-transition metal dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm2 V−1 s−1, much higher than that of the back-gated counterparts (∼1 cm2 V−1 s−1). Based on a direct-coupled FET logic technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of 3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and integration properties make monolayer SnS2 a strong candidate for next-generation atomic electronics.
TL;DR: In this paper, the authors performed a combined experimental and theoretical study on atomically thin MoS2 field effect transistors with varying the number of MoS 2 layers (NLs).
Abstract: Two-dimensional semiconductors are structurally ideal channel materials for the ultimate atomic electronics after silicon era. A long-standing puzzle is the low carrier mobility (μ) in them as compared with corresponding bulk structures, which constitutes the main hurdle for realizing high-performance devices. To address this issue, we perform a combined experimental and theoretical study on atomically thin MoS2 field effect transistors with varying the number of MoS2 layers (NLs). Experimentally, an intimate μ–NL relation is observed with a 10-fold degradation in μ for extremely thinned monolayer channels. To accurately describe the carrier scattering process and shed light on the origin of the thinning-induced mobility degradation, a generalized Coulomb scattering model is developed with strictly considering device configurative conditions, that is, asymmetric dielectric environments and lopsided carrier distribution. We reveal that the carrier scattering from interfacial Coulomb impurities (e.g., chemi...
TL;DR: In this paper, the electrical characteristics of field effect transistors (FETs) with single-crystal molybdenum disulfide (MoS2) channels synthesized by chemical vapor deposition (CVD) were reported.
Abstract: We report the electrical characteristics of field-effect transistors (FETs) with single-crystal molybdenum disulfide (MoS2) channels synthesized by chemical vapor deposition (CVD). For a bilayer MoS2 FET, the field-effect mobility is ∼17 cm2 V−1 s−1 and the on/off current ratio is ∼108, which are much higher than those of FETs based on CVD polycrystalline MoS2 films. By avoiding the detrimental effects of the grain boundaries and the contamination introduced by the transfer process, the quality of the CVD MoS2 atomic layers deposited directly on SiO2 is comparable to or better than the exfoliated MoS2 flakes. The result shows that CVD is a viable method to synthesize high quality MoS2 atomic layers.
TL;DR: PbSe quantum dot (QD) field effect transistors (FETs) with air-stable electron mobilities above 7 cm(2) V (-1) s(-1) are made by infilling sulfide-capped QD films with amorphous alumina using low-temperature atomic layer deposition (ALD).
Abstract: PbSe quantum dot (QD) field effect transistors (FETs) with air-stable electron mobilities above 7 cm2 V–1 s–1 are made by infilling sulfide-capped QD films with amorphous alumina using low-temperature atomic layer deposition (ALD). This high mobility is achieved by combining strong electronic coupling (from the ultrasmall sulfide ligands) with passivation of surface states by the ALD coating. A series of control experiments rule out alternative explanations. Partial infilling tunes the electrical characteristics of the FETs.
TL;DR: In this paper, it is demonstrated that nanomembranes of the widebandgap semiconductor gallium oxide can be used as channels of transistors capable of switching high voltages, and at the same time can be integrated on any platform.
Abstract: Nanoscale semiconductor materials have been extensively investigated as the channel materials of transistors for energy-efficient low-power logic switches to enable scaling to smaller dimensions. On the opposite end of transistor applications is power electronics for which transistors capable of switching very high voltages are necessary. Miniaturization of energy-efficient power switches can enable the integration with various electronic systems and lead to substantial boosts in energy efficiency. Nanotechnology is yet to have an impact in this arena. In this work, it is demonstrated that nanomembranes of the wide-bandgap semiconductor gallium oxide can be used as channels of transistors capable of switching high voltages, and at the same time can be integrated on any platform. The findings mark a step towards using lessons learnt in nanomaterials and nanotechnology to address a challenge that yet remains untouched by the field.
TL;DR: In this article, polyethyleneimine (PEI) doping on multilayer MoS2 field-effect transistors is investigated, and the authors demonstrate the feasibility of PEI molecular doping in MoS 2 transistors and its potential applications in layer-structured semiconducting 2D crystals.
Abstract: For the first time, polyethyleneimine (PEI) doping on multilayer MoS2 field-effect transistors is investigated. A 2.6 times reduction in sheet resistance and 1.2 times reduction in contact resistance have been achieved. The enhanced electrical characteristics are also reflected in a 70% improvement in ON-current and 50% improvement in extrinsic field-effect mobility. The threshold voltage confirms a negative shift upon the molecular doping. All studies demonstrate the feasibility of PEI molecular doping in MoS2 transistors and its potential applications in layer-structured semiconducting 2-D crystals.
TL;DR: In this paper, stacked field effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors.
Abstract: Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage $Q$ -band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 $\mu$ m $\,\times\,$ 500 $\mu$ m including pads.
TL;DR: The findings suggest that in a multilayer MoS2 field-effect transistor the "HOT-SPOT" of the current flow migrates dynamically between the layers as a function of the applied back gate bias and manifests itself in a rather unusual "contact resistance" that cannot be explained using the conventional models for metal-to-semiconductor contacts.
Abstract: In this Letter, we map for the first time the current distribution among the individual layers of multilayer two-dimensional systems. Our findings suggest that in a multilayer MoS2 field-effect transistor the “HOT-SPOT” of the current flow migrates dynamically between the layers as a function of the applied back gate bias and manifests itself in a rather unusual “contact resistance” that cannot be explained using the conventional models for metal-to-semiconductor contacts. To interpret this unique contact resistance, extracted from a channel length scaling study, we employed a resistor network model based on Thomas–Fermi charge screening and interlayer coupling. By modeling our experimental data we have found that the charge screening length for MoS2 is rather large (λMoS2 = 7 nm) and translates into a current distribution in multilayer MoS2 systems, which is distinctly different from the current distribution in multilayer graphene (λgraphene = 0.6 nm). In particular, our experimental results allow us to ...
TL;DR: In this article, Molybdenum disulfide (MoS2) field effect transistors (FETs) were fabricated on atomically smooth large-area single layers grown by chemical vapor deposition.
Abstract: Molybdenum disulfide (MoS2) field effect transistors (FET) were fabricated on atomically smooth large-area single layers grown by chemical vapor deposition. The layer qualities and physical properties were characterized using high-resolution Raman and photoluminescence spectroscopy, scanning electron microscopy, and atomic force microscopy. Electronic performance of the FET devices was measured using field effect mobility measurements as a function of temperature. The back-gated devices had mobilities of 6.0 cm2/V s at 300 K without a high-κ dielectric overcoat and increased to 16.1 cm2/V s with a high-κ dielectric overcoat. In addition the devices show on/off ratios ranging from 105 to 109.
TL;DR: In this paper, the authors review past reports on the metal halide semiconductor CuI and related alloys and discuss recent progress with regard to this material including its use in organic electronics and solar cells as well as their own work on fully transparent bipolar heterostructure diodes (p-CuI/n-ZnO).
Abstract: Halide semiconductors stand at the very beginning of semiconductor science and technology. CuI was reported as the first transparent conductor, and the first field effect transistor was made from KBr. Although halogens are frequently used in semiconductor preparation, little use is currently made from halide semiconductors in electronics and photonics. We review past reports on the metal halide semiconductor CuI and related alloys and discuss recent progress with regard to this material including its use in organic electronics and solar cells as well as our own work on fully transparent bipolar heterostructure diodes (p-CuI/n-ZnO) with high rectification of several 107 and ideality factors down to 1.5.
γ-CuI(111) thin film on glass (1 × 1 cm2) and IV-characteristics of p-CuI/n-ZnO/a-Al2O3 bipolar heterojunction diode.
TL;DR: In this paper, polyethyleneimine (PEI) doping on multilayer MoS2 field-effect transistors is investigated, and a 2.6 times reduction in sheet resistance and 1.2 times reduction of contact resistance have been achieved.
Abstract: For the first time, polyethyleneimine (PEI) doping on multilayer MoS2 field-effect transistors are investigated. A 2.6 times reduction in sheet resistance, and 1.2 times reduction in contact resistance have been achieved. The enhanced electrical characteristics are also reflected in a 70% improvement in ON current, and 50% improvement in extrinsic field-effect mobility. The threshold voltage also confirms a negative shift upon the molecular doping. All studies demonstrate the feasibility of PEI molecular doping in MoS2 transistors, and its potential applications in layer-structured semiconducting 2D crystals.
TL;DR: This Letter synthesizes monolayer MoS2 on Si/SiO2 substrate via chemical vapor deposition (CVD) method and comprehensively study the device performance based on dual-gatedMoS2 field-effect transistors.
Abstract: Monolayer molybdenum disulfide (MoS2) with a direct band gap of 1.8 eV is a promising two-dimensional material with a potential to surpass graphene in next generation nanoelectronic applications. In this Letter, we synthesize monolayer MoS2 on Si/SiO2 substrate via chemical vapor deposition (CVD) method and comprehensively study the device performance based on dual-gated MoS2 field-effect transistors. Over 100 devices are studied to obtain a statistical description of device performance in CVD MoS2. We examine and scale down the channel length of the transistors to 100 nm and achieve record high drain current of 62.5 mA/mm in CVD monolayer MoS2 film ever reported. We further extract the intrinsic contact resistance of low work function metal Ti on monolayer CVD MoS2 with an expectation value of 175 Ω·mm, which can be significantly decreased to 10 Ω·mm by appropriate gating. Finally, field-effect mobilities (μFE) of the carriers at various channel lengths are obtained. By taking the impact of contact resis...
TL;DR: Both a highly crystalline conjugated polymer layer and very smooth insulating polymer layer are formed by a consecutive wire-bar-coating process on a 4-inch plastic substrate with a short processing time for application as the active and dielectric layers of OFET arrays and ICs.
Abstract: Solution-processed organic semiconductors are of great potential for large-area, inexpensive, lightweight, and fl exible electronic applications. With respect to these materials, tremendous effort has recently been focused on developing several types of organic electronic and optoelectronic devices, such as organic light-emitting diodes (OLEDs), organic photovoltaics (OPVs), organic fi eld-effect transistors (OFETs), and organic memory and sensors, using graphic-art printing methods on fl substrates. [ 1‐5 ] OFETs are a fundamental building block of integrated circuits (ICs) and drivers for active-matrix fl at-panel displays. Accordingly, they are a promising candidate to replace the vacuum-processed amorphous inorganic ICs; this would enable the use of drivers in printed and fl exible radio-frequency identifi cation tags, memories, sensors, and display backplanes. [ 6 , 7 ] To realize high-speed organic printed ICs, the complementary IC geometry, which consists of p- and n-channel transistors, has an advantage over those that comprise unipolar transistors because of reduced transition delays, higher noise immunity, and negligible power consumption in the static state. [ 8 ] In solution-processed devices, p- and n-type active channels have been patterned at resolutions as low as a few micrometers using a variety of printing methods such as inkjet, spray, and gravure printing. [ 9 ] However, these printing processes typically result in device-to-device performance deviations because of diffi culties inherent in controlling the morphology (e.g., roughness and crystallinity) of micrometre-sized deposits. For example, organic semiconductor droplets that are deposited via ink jet onto non-absorbing substrates typically show signifi cant coffee
TL;DR: This study will be helpful in understanding the electrical-stress-induced instability of the MoS2-based electronic devices and will also give insight into the design of desirable devices for electronics applications.
Abstract: We investigated the gate bias stress effects of multilayered MoS2 field effect transistors (FETs) with a back-gated configuration. The electrical stability of the MoS2 FETs can be significantly influenced by the electrical stress type, relative sweep rate, and stress time in an ambient environment. Specifically, when a positive gate bias stress was applied to the MoS2 FET, the current of the device decreased and its threshold shifted in the positive gate bias direction. In contrast, with a negative gate bias stress, the current of the device increased and the threshold shifted in the negative gate bias direction. The gate bias stress effects were enhanced when a gate bias was applied for a longer time or when a slower sweep rate was used. These phenomena can be explained by the charge trapping due to the adsorption or desorption of oxygen and/or water on the MoS2 surface with a positive or negative gate bias, respectively, under an ambient environment. This study will be helpful in understanding the electrical-stress-induced instability of the MoS2-based electronic devices and will also give insight into the design of desirable devices for electronics applications.
TL;DR: In this paper, electrical gating of photoluminescence and optical absorption in monolayer molybdenum disulfide (MoS2) configured in field effect transistor geometry was investigated.
TL;DR: The R-GO FET biosensor showed a high specificity to other cancer biomarker in the phosphate buffered saline solutions as well as in the human serum, and can detect protein-protein interactions down to femtomolar level with a dynamic range over 6-orders of magnitude in the V(g,min) shift as a sensitivity parameter.
TL;DR: In this article, the first uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field effect transistors (TFETs) are fabricated.
Abstract: Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.
TL;DR: A sensitive and selective field-effect transistor (FET) biosensor is demonstrated using vertically-oriented graphene (VG) sheets labeled with gold nanoparticle (NP)-antibody conjugates using a plasma-enhanced chemical vapor deposition (PECVD) method.
Abstract: A sensitive and selective field-effect transistor (FET) biosensor is demonstrated using vertically-oriented graphene (VG) sheets labeled with gold nanoparticle (NP)-antibody conjugates. VG sheets are directly grown on the sensor electrode using a plasma-enhanced chemical vapor deposition (PECVD) method and function as the sensing channel. The protein detection is accomplished through measuring changes in the electrical signal from the FET sensor upon the antibody-antigen binding. The novel biosensor with unique graphene morphology shows high sensitivity (down to ~2 ng/ml or 13 pM) and selectivity towards specific proteins. The PECVD growth of VG presents a one-step and reliable approach to prepare graphene-based electronic biosensors.