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Showing papers on "Field-programmable gate array published in 1982"


Patent
Kenneth E Rhodes1
24 May 1982
TL;DR: In this paper, a technique for condensing the overall size of a PLA circuit and a number of circuit elements involved in carrying out a desired logical OR operation is described, which is done by preconditioning the product term in the AND array to be grounded and the source of the OR array elements to be connected to the positive potential, polarities which are opposite to those for the balance of the PLA circuit.
Abstract: A technique is disclosed for condensing the overall size of a PLA circuit and a number of circuit elements involved in carrying out a desired logical OR operation. This is done by preconditioning the product term in the AND array to be grounded and the source of the AND array elements to be connected to the positive potential, polarities which are opposite to those for the balance of the PLA circuit. Therefore, if the particular AND or search array term is selected by means of its gate going positive, the product term line output will rise in potential instead of failing. Since any search array element will have this effect in a column of elements, an OR logical function is performed in what is otherwise the AND array of the PLA. The resultant localized change in polarities achieves a significant reduction in the number of product term columns necessary to carry out an OR logical function in the conventional AND array of a PLA.

Patent
23 Mar 1982
TL;DR: In this article, a programmable, highly integrated logic circuit array (PLA), the two-personalized cells in the AND and in the OR array (1 and 2) are provided.
Abstract: There is provided a programmable, highly integrated logic circuit array (PLA), the two-personalized cells in the AND and in the OR array (1 and 2) (Fig. 2). To enable the otherwise redundant Do not Care positions, the AND array (1) control circuits (ST1 to STn) upstream, and also control circuits (STPO to STPN) between the AND array (1) and the OR array ( 2). These control circuits have a similar structure and consist of a two-stage AND-OR circuit. For optimum utilization of the Do not Care positions and levels of each function input can be routed to any function Fn strand of the PLAs. By an additional control line (eg S4) in the OR array 2, the control logic for the entire reduced OR array (2) on only two AND gates.