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Showing papers on "Field-programmable gate array published in 1990"


Journal ArticleDOI
TL;DR: It was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block.
Abstract: The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block. >

301 citations


Proceedings ArticleDOI
24 Jun 1990
TL;DR: An algorithm for technology mapping of combinational logic into Field Programmable Gate Arrays that use lookup table memories to realize combinational functions, implemented in a program called Chortle, which can determine the optimal mapping for fanout-free trees of comb multinational logic.
Abstract: Field Programmable Gate Arrays are new devices that combine the versatility of a Gate Array with the user-programmability of a PAL. This paper describes an algorithm for technology mapping of combinational logic into Field Programmable Gate Arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions, and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle uses the fact that a K-input lookup table can implement any Boolean function of K-inputs, and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparisons with the MIS II technology mapper, on MCNC-89 Logic Synthesis benchmarks Chortle achieves superior results in significantly less time. 1

181 citations


Proceedings ArticleDOI
13 May 1990
TL;DR: Using a combination of architectural and process improvements, a third-generation family of field-programmable gate arrays (FPGAs) features up to twice the density and speed of currently-available FPGA devices.
Abstract: Using a combination of architectural and process improvements, a third-generation family of field-programmable gate arrays (FPGAs) features up to twice the density and speed of currently-available FPGA devices. The architecture was devised to allow complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. This architecture is described. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices. >

149 citations


Proceedings ArticleDOI
13 May 1990
TL;DR: The dynamically reconfigurable Plessey ERA (electrically reconfigured array), by supporting the paging of full and partial sets of configuration data at system clock speed, allows silicon multitasking and introduces the concept of the hardware subroutine.
Abstract: The dynamically reconfigurable Plessey ERA (electrically reconfigurable array), by supporting the paging of full and partial sets of configuration data at system clock speed, allows silicon multitasking and introduces the concept of the hardware subroutine. The ERA requires 2.5 times less data per equivalent gate as compared to the established industry standard devices. In addition, loading the data in parallel bytes at clock speeds up to 25 MHz reduces the time taken for the complete configuration of a 10000 equivalent gate array to less than 140 mu s. >

89 citations


Proceedings ArticleDOI
13 May 1990
TL;DR: In this paper, the relationship between the routability of a field programmable gate array (FPGA) and the flexibility of its interconnection structures is explored, and a set of industrial circuits are implemented as FPGAs in a range of routing structures with varying flexibility.
Abstract: The relationship between the routability of a field programmable gate array (FPGA) and the flexibility of its interconnection structures is explored. A set of industrial circuits are implemented as FPGAs in a range of routing structures with varying flexibility. Experiments indicate that high flexibility is essential for the connection box that joint the logic blocks to the routing channel, but a relatively low flexibility is sufficient for switch boxes at the junction of horizontal and vertical channels. >

27 citations


Proceedings ArticleDOI
04 Jun 1990
TL;DR: The Anyboard system reduces the time required to implement a design and avoids some of the problems associated with the use of wire-wrap or prototyping board implementations.
Abstract: A rapid prototyping system for teaching digital design is described. The system uses electronically-reconfigurable field programmable gate arrays (FPGAs) to implement a specific logic design without requiring any physical changes to the prototyping system. The user specifies designs using a text based description language. The prototyping system partitions the input logic among the available FPGA resources while observing constraints on gate density and chip I/O. The combinational logic blocks (CLBs) in each individual FPGA are then placed and the interconnections are routed. Once programmed, the system can be exercised using a pattern generator and logic analyzer. The Anyboard system reduces the time required to implement a design and avoids some of the problems associated with the use of wire-wrap or prototyping board implementations. >

13 citations


01 Sep 1990
TL;DR: Two new algorithms for doing mapping from multi-level logic to field-programmable gate arrays, based on an if-then-else DAG representation of the functions, are presented.
Abstract: This paper presents two new algorithms for doing mapping from multi-level logic to field-programmable gate arrays. One algorithm, Xmap, is for mapping to table-lookup gates (for example, the Xilinx chip); the other, Amap, is for mapping to selector-based architectures (for example, the Actel chip). Mapping to the Actel architecture can also be achieved by mapping to 3-input tables, and replacing them with equivalent Actel cells (XAmap). The algorithms are based on an if-then-else DAG representation of the functions. The technology mappers differ from previous mappers in that the circuit is not decomposed into fan-out-free trees. The gate counts and CPU time are compared with three previous mappers for these architectures: misII, Chortle, and mis-pga. The Xmap algorithm for table-lookup architectures gets 7\% fewer cells than Chortle, 11\% fewer than misII, and 14\% fewer than mis-pga, and is 4.5 times faster than Chortle, 17 times faster than misII, and at least 150 times faster than mis-pga. The Amap algorithm for Actel cells use 6\% fewer cells than misII and about 8\% more cells than the best achieved by mis-pga, and is at least 25 times as fast as misII and at least 586 times as fast as mis-pga.

13 citations


Proceedings ArticleDOI
17 Sep 1990
TL;DR: ASIC in-circuit emulation technology for validation of embedded core ASICs in target systems is described, which creates a gate-by-gate, wire- by-wire replica of an ASIC design onto real hardware to validate the system design with full software and applications before actually committing to silicon.
Abstract: ASIC in-circuit emulation technology for validation of embedded core ASICs in target systems is described. The emulation system contains an array of reprogrammable logic devices. Any ASIC vendor netlist can be accepted by the software. It is automatically partitioned, placed, and routed on the array of reprogrammable logic devices, called the emulation modules. The system creates a gate-by-gate, wire-by-wire replica of an ASIC design onto real hardware. In-circuit interface cables connect the functional image of the ASIC to the target system. This allows the designer to plug the ASIC design into the target system prior to having silicon built. The advantage is validation of the system design with full software and applications before actually committing to silicon. This makes design tradeoffs possible at an earlier stage. The built-in logic analyzer allows the designer to debug the ASIC design while running in-circuit, much like a microprocessor in-circuit emulator. >

8 citations


Proceedings ArticleDOI
17 Sep 1990
TL;DR: The management of risk and the economic advantage of using reprogrammable hardware emulation in the ASIC design cycle is studied.
Abstract: ASIC design validation, confirming that the chips work in the system, has been the major source of risk in any ASIC development cycle. The risk is that of missing the market window. The cause is the lack of technologies to assure, before fabrication, that ASIC designs will operate properly in the target system. Innovations in the area of field programmable gate arrays have enabled an ASIC system design tool technology called reprogrammable hardware emulation. The management of risk and the economic advantage of using this technology in the ASIC design cycle is studied. >

3 citations


Proceedings ArticleDOI
17 Sep 1990
TL;DR: The MACH (macro array CMOS high performance) family of programmable logic devices (PLDs) is described in this article, combining an innovative and optimized silicon architecture with an advanced 0.8 mu m double-metal, electrically erasable CMOS technology, the MACH family offers the speed of low-end programmable array logic (PAL) devices (15 ns propagation delays), with the density of field programmable gate arrays (900 to 3600 equivalent gate densities).
Abstract: The MACH (macro array CMOS high performance) family of programmable logic devices (PLDs) is described. Combining an innovative and optimized silicon architecture with an advanced 0.8 mu m double-metal, electrically erasable CMOS technology, the MACH family offers the speed of low-end programmable array logic (PAL) devices (15 ns propagation delays), with the density of field programmable gate arrays (900 to 3600 equivalent gate densities), providing 3 to 12 times the functionality of existing PLD solutions. >

3 citations


Journal ArticleDOI
T.K. Koelling1
TL;DR: The use of the combinational/register coordinate system as a graphical way of measuring programmable logic devices (PLDs) in terms of gates and registers is reviewed and methods for calculating the application range are described.
Abstract: The use of the combinational/register coordinate system as a graphical way of measuring programmable logic devices (PLDs) in terms of gates and registers is reviewed. It is assumed that the I/O resources of the PLD, which constitute a third axis, are adequate. This allows the analysis to be restricted to an x-y plane fixed along the z-axis. The device's application area, which is the area bounded by its combinational and register capability, is discussed, and methods for calculating the application range are described. Three brief examples demonstrate the ways in which the coordinate system might be used in CAD tools that automate the PLD design process. >

Proceedings ArticleDOI
17 Sep 1990
TL;DR: The ASIC education program at the Tampere University of Technology is discussed and hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level.
Abstract: The ASIC education program at the Tampere University of Technology is discussed. The design tools, educational activities, and foundry services are described. Hardware description languages and system-level simulations are adopted from basic design courses to shift the emphasis in education from layout-level descriptions towards ASIC system oriented designs at undergraduate level. Silicon foundry services through FINCHIP, NORCHIP, and EUROCHIP with field programmable gate array structures from Xilinx and Actel are utilized. >

Proceedings ArticleDOI
17 Sep 1990
TL;DR: This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture and supports hierarchical designs by general schematic entries and functional description entries.
Abstract: This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries. >

Proceedings ArticleDOI
R.B. Ravel1
17 Sep 1990
TL;DR: A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed.
Abstract: A third-generation family of field-programmable gate arrays (FPGAs) that utilizes a combination of architectural and process improvements and features up to twice the density and speed of currently available FPGA devices is discussed. The architecture allows complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices. >