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Flash ADC

About: Flash ADC is a research topic. Over the lifetime, 1811 publications have been published within this topic receiving 19821 citations.


Papers
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Journal ArticleDOI
TL;DR: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller.
Abstract: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

377 citations

Journal ArticleDOI
01 Dec 2001
TL;DR: In this paper, a 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz using array averaging and a wideband track-and-hold is reported.
Abstract: A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.

275 citations

Proceedings ArticleDOI
01 Feb 2008
TL;DR: This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR because it uses a comparator, named time-domainComparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
Abstract: The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.

241 citations

Journal ArticleDOI
TL;DR: A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS to improve dynamic performance, and comparator offset calibration to reduce power dissipation.
Abstract: This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.

241 citations

Proceedings ArticleDOI
18 Sep 2006
TL;DR: A high-speed 4b flash ADC in 90nm digital CMOS is presented that uses a dynamic offset-compensation scheme in its comparators that achieves a sampling rate of 1.25GS/s with 3.7 ENOB (23.8dB SNDR) from dc to Nyquist while consuming 2.5mW.
Abstract: A high-speed 4b flash ADC in 90nm digital CMOS is presented that uses a dynamic offset-compensation scheme in its comparators. It achieves a sampling rate of 1.25GS/s with 3.7 ENOB (23.8dB SNDR) from dc to Nyquist while consuming 2.5mW. It has an energy per conversion step of 0.16pJ

221 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202320
202265
202134
202042
201952
201869