scispace - formally typeset
Search or ask a question
Topic

Flash memory

About: Flash memory is a research topic. Over the lifetime, 18175 publications have been published within this topic receiving 244965 citations.


Papers
More filters
Journal ArticleDOI
TL;DR: In this paper, the authors review the current status of one of the alternatives, resistance random access memory (ReRAM), which uses a resistive switching phenomenon found in transition metal oxides.

2,641 citations

Journal ArticleDOI
TL;DR: This work demonstrates a TaO(x)-based asymmetric passive switching device with which it was able to localize resistance switching and satisfy all aforementioned requirements, and eliminates any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.
Abstract: Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

1,900 citations

Journal ArticleDOI
TL;DR: In this paper, a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation is presented, which is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction.
Abstract: This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250/spl deg/C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 /spl mu/m process, the area of a bit is 0.315 /spl mu/m/sup 2/ and 0.188 /spl mu/m/sup 2/ in 0.25 /spl mu/m technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.

1,170 citations

Journal ArticleDOI
21 May 2003
TL;DR: The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible and an insight into the multilevel approach, where two bits are stored in the same cell, is presented.
Abstract: This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

943 citations

Journal ArticleDOI
TL;DR: This work proposes a novel FTL design that combines the two different granularities in address translation, motivated by the idea that coarse grain address translation lowers the resources required to maintain translation information, which is crucial in mobile consumer products for cost and power consumption reasons, while fine grain addresstranslation is efficient in handling small size writes.
Abstract: Flash memory is becoming increasingly important as nonvolatile storage for mobile consumer electronics due to its low power consumption and shock resistance. However, it imposes technical challenges in that a write should be preceded by an erase operation, and that this erase operation can be performed only in a unit much larger than the write unit. To address these technical hurdles, an intermediate software layer called a flash translation layer (FTL) is generally employed to redirect logical addresses from the host system to physical addresses in flash memory. Previous approaches have performed this address translation at the granularity of either a write unit (page) or an erase unit (block). We propose a novel FTL design that combines the two different granularities in address translation. This is motivated by the idea that coarse grain address translation lowers the resources required to maintain translation information, which is crucial in mobile consumer products for cost and power consumption reasons, while fine grain address translation is efficient in handling small size writes. Performance evaluation based on trace-driven simulation shows that the proposed scheme significantly outperforms previously proposed approaches.

927 citations


Network Information
Related Topics (5)
Transistor
138K papers, 1.4M citations
89% related
CMOS
81.3K papers, 1.1M citations
88% related
Integrated circuit
82.7K papers, 1M citations
87% related
Field-effect transistor
56.7K papers, 1M citations
85% related
Capacitance
69.6K papers, 1M citations
82% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202356
2022139
2021175
2020424
2019619
2018584