Flip chip

About: Flip chip is a research topic. Over the lifetime, 16009 publications have been published within this topic receiving 219696 citations.

Six cases of reliability study of Pb-free solder joints in electronic packaging technology

Abstract: Solder is widely used to connect chips to their packaging substrates in flip chip technology as well as in surface mount technology. At present, the electronic packaging industry is actively searching for Pb-free solders due to environmental concern of Pb-based solders. Concerning the reliability of Pb-free solders, some electronic companies are reluctant to adopt them into their high-end products. Hence, a review of the reliability behavior of Pb-free solders is timely. We use the format of “case study” to review six reliability problems of Pb-free solders in electronic packaging technology. We conducted analysis of these cases on the basis of thermodynamic driving force, time-dependent kinetic processes, and morphology and microstructure changes. We made a direct comparison to the similar problem in SnPb solder whenever it is available. Specifically, we reviewed: (1) interfacial reactions between Pb-free solder and thick metalliztion of bond-pad on the substrate-side, (2) interfacial reactions between Pb-free solder and thin-film under-bump metallization on the chip-side, (3) the growth of a layered intermetallic compound (IMC) by ripening in solid state aging of solder joints, (4) a long range interaction between chip-side and substrate-side metallizations across a solder joint, (5) electromigration in flip chip solder joints, and finally (6) Sn whisker growth on Pb-free finish on Cu leadframe. Perhaps, these cases may serve as helpful references to the understanding of other reliability behaviors of Pb-free solders.

Recent advances on electromigration in very-large-scale-integration of interconnects

Abstract: Today, the price of building a factory to produce submicron size electronic devices on 300 mm Si wafers is over billions of dollars. In processing a 300 mm Si wafer, over half of the production cost comes from fabricating the very-large-scale-integration of the interconnect metallization. The most serious and persistent reliability problem in interconnect metallization is electromigration. In the past 40 years, the microelectronic industry has used Al as the on-chip conductor. Due to miniaturization, however, a better conductor is needed in terms of resistance–capacitance delay, electromigration resistance, and cost of production. The industry has turned to Cu as the on-chip conductor, so the question of electromigration in Cu metallization must be examined. On the basis of what we have learned from the use of Al in devices, we review here what is current with respect to electromigration in Cu. In addition, the system of interconnects on an advanced device includes flip chip solder joints, which now tend ...

Semiconductor wafer bonding

Abstract: When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical devices. The basics of wafer-bonding technology are described, including microcleanroom approaches, prevention of interface bubbles, bonding of III-V compounds, low-temperature bonding, ultra-high vacuum bonding, thinning methods such as smart-cut procedures, and twist wafer bonding for compliant substrates. Wafer bonding allows a new degree of freedom in design and fabrication of material combinations that previously would have been excluded because these material combinations cannot be realized by the conventional approach of epitaxial growth.

Tin–lead (SnPb) solder reaction in flip chip technology

Abstract: Solder reactions between SnPb and one of the four metals, Cu, Ni, Au, and Pd have been reviewed on the basis of the available data of morphology, thermodynamics, and kinetics. The reactions on both bulk and thin film forms of these metals have been considered and compared. Also the two kinds of reactions, above and below the melting point of the solder, have been considered and compared. The rate of intermetallic compound formation in wetting reactions between the molten solder and the metals is three to four orders of magnitude faster than those between the solid state solder and the metals. The rate is controlled by the morphology of intermetallic compound formation. In the wetting reaction between molten SnPb and Cu or Ni, the intermetallic compound formation has a scallop-type morphology, but in solid state aging, it has a layer-type morphology. There are channels between the scallops, which allow rapid diffusion and rapid rate of compound formation. In the layer-type morphology, the compound layer itself becomes a diffusion barrier to slow down the reaction. Similar morphological changes occur between SnPb and Au or Pd. The stability of scallop-type morphology in wetting reaction and layer-type morphology in solid state aging have been explained by minimization of surface and interfacial energies. The unusually high rate of scallop-type intermetallic compound formation has been explained by the gain of rate of free energy change rather than free energy change. Also included in the review is the use of a stack of thin films as under-bump-metallization, such as Cr/Cu/Au, Al/Ni(V)/Cu, and Cu/Ni alloyed thin films.

Semiconductor flip-chip package and method for the fabrication thereof

Abstract: A simplified process for flip-chip attachment of a chip (10) to a substrate (20) is provided by pre-coating the chip (10) with an encapsulant underfill material (22) having discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip (10) and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip (10) and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps (14) on the chip are fully in contact with the substrate (20). There is provided a flip-chip configuration having a compliant solder/flexible encapsulant understructure that deforms generally laterally with the substrate (20) as the substrate (20) undergoes expansion and contraction. With this configuration, the compliant solder/flexible encapsulant understructure absorbs the strain caused by the substrate without bending the chip (10) and substrate (20).