About: Flip-flop is a(n) research topic. Over the lifetime, 2543 publication(s) have been published within this topic receiving 20692 citation(s).
Papers published on a yearly basis
TL;DR: The design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented and it is found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage.
Abstract: Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.
08 Feb 1996
TL;DR: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load.
Abstract: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.
•27 Feb 1985
TL;DR: A configurable logic circuit achieves versatility by including a configurable combinational logic element, configurable storage circuit, and configurable output select logic as discussed by the authors, which can be configured to operate as a D flip flop, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector.
Abstract: A configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip flop with or without set and reset inputs, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output signals from among the output signals of the combinational logic element and the storage circuit.
31 Jan 2003
TL;DR: In this paper, a 3-state inverter is combined with a transparent latch to produce a transparent-latch circuit, which can then be used as a basis for constructing a wide variety of useful, state-maintaining circuits, all implementable within molecular junction-nanowire crossbars.
Abstract: Methods for implementing familiar electronic circuits at nanoscale sizes using molecular-junction-nanowire crossbars, and nanoscale electronic circuits produced by the methods. In one embodiment of the present invention, a 3-state inverter is implemented. In a second embodiment of the present invention, two 3-state inverter circuits are combined to produce a transparent latch. The 3-state inverter circuit and transparent-latch circuit can then be used as a basis for constructing additional circuitry, including master/slave flip-flops, a transparent latch with asynchronous preset, a transparent latch with asynchronous clear, and a master/slave flip-flop with asynchronous preset. 3-state inverters can thus be used to compose latches and flip-flops, and latches and flip-flops can be used, along with additional Boolean circuitry, to compose a wide variety of useful, state-maintaining circuits, all implementable within molecular-junction-nanowire crossbars by selectively configuring junctions within the molecular-junction-nanowire crossbars.
TL;DR: In this paper, the effects of Miller coupling and thermal noise on a synchronizing flip-flop are described and a worst case mean-time-between-failure bound is established.
Abstract: The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.
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