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Showing papers on "Flip-flop published in 1968"


Patent
08 Nov 1968
TL;DR: In this paper, a circuit capable of J-K operation and composed of enhancement type MOS transistors adapted for integrated circuits is presented, which avoids series connection by connecting one of the cross-connected feedback paths of each flip-flop assembly through a transmission transistor gated by the clock pulses.
Abstract: A circuit capable of J-K operation and composed of enhancementtype MOS transistors adapted for integrated circuits. The total gate area required for the transistors is reduced by minimization of series connection of two or more of the inverter transistors, which are required to have a low resistance compared with the transistors that perform a load resistor function. This avoidance of series connection is achieved by connecting one of the cross-connected feedback paths of each flip-flop assembly through a transmission transistor gated by the clock pulses.

11 citations


Patent
06 Dec 1968
TL;DR: A master-slave type J-K flip-flop circuit consisting of a master flip flop circuit and a slave flipflop is described in this article, where the master flipflops produce outputs Qm, Qm and the slave flips flop produces outputs Qs, Qs.
Abstract: A master-slave type J-K flip-flop circuit comprising a master flip-flop circuit-producing outputs Qm, Qm and a slave flip-flop circuit-producing outputs Qs, Qs. The master flip-flop The master flip-flop circuit includes a first set input circuit having a current-switching type logical circuit which performs an AND operation of an input J and clock Cp in reference to the output Qs and a first reset input circuit having a current-switching type logical circuit which performs and AND operation of an input K and clock Cp in reference to the output Qs. The slave flip-flop circuit includes a second set input circuit having a currentswitching type logical circuit which executes a current-switching operation of the clock Cp in reference to the output Qm and a second reset input circuit having a current-switching type logical circuit which executes a current-switching operation of the clock Cp in reference to the output Qm.

5 citations


Patent
05 Dec 1968
TL;DR: In this paper, a current switching-type flip-flop circuit is described, where a first and second sections each comprising a first currentswitching-type logic circuit consisting of a first transistor forming an AND input gate and a second transistor carrying out current switching operation jointly therewith, with a third transistor formed an OR input gate to perform flipflop action and a means for jointly connecting the collectors of the aforementioned second and third transistors.
Abstract: A current-switching-type flip-flop circuit device including first and second sections each comprising a first currentswitching-type logic circuit comprising a first transistor forming an AND input gate and a second transistor carrying out a current switching operation jointly therewith, a second currentswitching-type logic circuit provided with a third transistor forming an OR input gate to perform a flip-flop action, and a means for jointly connecting the collectors of the aforementioned second and third transistors.

5 citations


Patent
05 Apr 1968
TL;DR: In this article, a flip-flop circuit is provided with cross-coupling using an extra transistor between an input element and a circuit point directly responsive to the inverted signal of the opposite stage.
Abstract: A flip-flop circuit is provided with cross-coupling using an extra transistor between an input element and a circuit point directly responsive to the inverted signal of the opposite stage. Greater speed, symmetry and ease of formation in integrated circuits are achieved.

5 citations


Patent
01 Mar 1968
TL;DR: In this article, a bistable flip-flop circuit for use in monolithic semiconductor integrated circuits with a master flipflop at the circuit input and a slave output was presented.
Abstract: A bistable flip-flop circuit for use preferably in monolithic semiconductor integrated circuits having a master flip-flop at the circuit input and a slave output at the circuit output with coupling transistors between the two master and slave flip-flops. The emitters of the transistors coupled through a resistor to the clock pulse input so that the master flip-flop changes state responsive to the rise time of the clock pulse and the slave flip-flop changes state during the fall time of the clock pulse throughout an extended temperature range.

3 citations


Journal ArticleDOI
01 Feb 1968
TL;DR: In this paper, a flip-flop circuit with dynamic storage of the original flip flop pulses is presented. But the circuit is not shown to be stable and stability of the circuit was demonstrated by the absence of time jitter.
Abstract: Time differences are measured after dynamic storage of the original flip-flop pulses and are stretched by a factor exceeding 250. Stability of the circuit is demonstrated by the absence of time jitter. The circuit presented apparently shows considerable advantages over devices applying digital counters.