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Showing papers on "Flip-flop published in 1971"


Patent
19 Apr 1971
TL;DR: In this article, a noise-immune pulse-forming circuit with a flip flop is described, which has a time-determining capacitor which has nearly no voltage across it in quiescent state.
Abstract: A noise-immune pulse-forming circuit which is a monostable multivibrator having a diode for dynamic feedback. A flip flop follows the diode. A timing circuit has a time-determining capacitor which has nearly no voltage across it in the quiescent state. The timing circuit resets the flip flop via one input of a differential amplifier.

16 citations


Patent
Clapper Steven Lynn1
23 Aug 1971
TL;DR: In this article, a flip-flop circuit utilizing insulated gate field effect transistors in a plurality of AND, NOR and inverter circuits connected to receive a signal and the inverse thereof on two inputs and to supply an output signal, the outputs being resettable to specific levels upon the application of a reset signal to a reset input.
Abstract: A bistable flip-flop circuit utilizing insulated gate field effect transistors in a plurality of AND, NOR and inverter circuits connected to receive a signal and the inverse thereof on two inputs and to supply an output signal and the inverse thereof on two outputs, the outputs being resettable to specific levels upon the application of a reset signal to a reset input.

12 citations


Patent
10 Nov 1971
TL;DR: In this paper, a state retention mechanism for a flip-flop was proposed for protecting the logic circuitry from radiation induced photocurrents during periods of transient ionizing pulses of a predetermined magnitude.
Abstract: A state retention apparatus for a radiation hardened flip flop for protecting the logic circuitry from radiation induced photocurrents. During periods of transient ionizing pulses of a predetermined magnitude, a switching function is performed to protect the logic state of the flip-flop and after the transients have decayed below a predetermined level, the flip-flop is returned to normal operation.

10 citations


Patent
Borgini Fred1
30 Nov 1971
TL;DR: In this article, the clock pulse terminals of a flip-flop cause it successively to change state, and a set pulse or reset pulse may be applied concurrently with a clock pulse which tends to place the flipflop in a state different than the state intended by the set or reset pulses.
Abstract: Successive clock pulses applied to the clock pulse terminals of a flip-flop cause it successively to change state. A set pulse or reset pulse may be applied to the flip-flop concurrently with a clock pulse which tends to place the flip-flop in a state different than the state intended by the set or reset pulse. The present circuit includes means responsive to the set or reset pulse for preventing the clock pulse from having any effect on the flip-flop. The means may comprise a logic gate to which the clock pulses are applied, storage means for priming the gate when charged, and means responsive to a set or reset pulse for discharging the storage means.

10 citations


Patent
Harold R Hensen1
03 May 1971
TL;DR: In this article, a timing circuit turns a flip-flop on and off to correspond to the beginning and end of a pulse, and a monostable multivibrator causes the break contacts to open and end the pulse.
Abstract: Pulse signals are produced by serially connected make and break contacts of respective relays. A timing circuit turns a flip-flop on and off to correspond to the beginning and end of a pulse. When the flip-flop is turned on, the make contacts are closed to initiate a pulse and when the flip-flop is turned off, a monostable multivibrator causes the break contacts to open and end the pulse. The timing circuit includes an on selecting circuit and an off selecting circuit which operates independently of each other.

7 citations


Patent
William P Buyak1
23 Mar 1971
TL;DR: In this paper, a circuit utilizing a unijunction transistor or equivalent relaxation oscillator with a flip flop connected to the output thereof and having its output connected to control the time constant of the relaxation oscillators so that on alternate oscillations the time constants will be relatively low and on the remaining oscillations it would be relatively high to generate a signal having two time intervals in succession.
Abstract: A circuit utilizing a unijunction transistor or equivalent relaxation oscillator with a flip flop connected to the output thereof and having its output connected to control the time constant of the relaxation oscillator so that on alternate oscillations the time constant will be relatively low and on the remaining oscillations it will be relatively high to generate a signal having two time intervals in succession. A logic network controls driving circuits in response to the signals produced by the oscillator and the logic circuit divides the frequency of the oscillations to values suitable for timers such as interrupter timers for telephone systems.

5 citations


Patent
05 Mar 1971
TL;DR: In this article, the circuit and method of connecting a J-K flip-flop so that it will operate as a one-shot multivibrator comprising establishing a ''''set'''' input at a logic 0 and an appropriate J or K input for momentary operation in response to a clock input was described.
Abstract: The circuit and method of connecting a J-K flip-flop so that it will operate as a one-shot multivibrator comprising establishing a ''''set'''' input at a logic 0 and an appropriate J or K input at a logic 1 for momentary operation in response to a clock input.

1 citations


Patent
Kosei Nomiya1, Hazime Tsugihashi1
22 Jun 1971
TL;DR: A flip-flop circuit in which the input and output terminals of two transistorized switching stages are cross-coupled mutually through the emitter-base junctions of a pair of transistors and a trigger input signal is commonly applied to the collectors of said pair as mentioned in this paper.
Abstract: A flip-flop circuit in which the input and output terminals of two transistorized switching stages are cross-coupled mutually through the emitter-base junctions of a pair of transistors and a trigger input signal is commonly applied to the collectors of said pair of transistors, through a pair of carrier storage diodes.