Showing papers on "Flip-flop published in 1973"

Set-reset flip-flop

Abstract: A circuit for setting and resetting a bistable circuit includes first and second transistors directly connected to the input of the bistable circuit for selectively clamping the input to a first or a second voltage level for setting the bistable circuit to one state or resetting it to the other state. In a bistable circuit comprised of a master flip-flop coupled to a slave flipflop by a transmission fate, the set-reset circuit includes first and second transistors directly connected to the input of the master and also includes means for enabling said transmission gate concurrently with the torn on of said first or second transistors for transferring the output of the master to the slave.

Regenerating circuit for binary signals in the form of a keyed flip-flop

Abstract: A regenerating circuit for binary signals in the form of a keyed flip-flop with one labile and two stable points has at least two inverting amplifier stages, featuring feedback, in particular for the stored signals and for the read-out signals of integrated single transistor storage elements which form a storage field. The storage elements of the storage field are connected by way of a digit line to the regenerating circuit and the inverting amplifier stages may be adjusted into the region of the labile point of the circuit by means of a feedback device by way of an inverter stage or an odd number of inverter stages.

Flip-flop circuits utilizing insulated gate field effect transistors

Abstract: A flip-flop circuit utilizing insulated gate field effect transistors or MOS transistors and operating as a set dominant type or a reset dominant type includes a delayed logic circuitry having a three-input logic circuit comprised of an AND-NOR gate constituted by P and N channel MOS transistors, and P and N channel clocked MOS transistors for operating the logic circuit in synchronism with a clock signal and a complement thereof. The output of the delayed logic circuitry is reversed in polarity by a first complementary MOS inverter. The three-input logic circuit receives a first logical input through a second complementary MOS inverter, a second logical input, and the output of the flip-flop circuit.

Hybrid storage circuit

Abstract: A semiconductor storage cell operating on the flip flop principle and in which the cross-coupled storage transistors and the load transistors are field effect and bipolar transistors, respectively. The semiconductor cell is a FET storage cell whose active storage transistors are field effect transistors which, in contrast to bipolar transistors, do not have to be isolated against each other, thus occupying a smaller semiconductor area. The bipolar load transistors permit a very low stand-by current on the order of the leakage current to be impressed, which in contrast to FET load elements can be changed to a desirably high operating current during reading. Apart from this, the bipolar transistors in the load branches need not be isolated against each other in this configuration, so that at a low rate of permanent power dissipation, which is roughly comparable to that of CMOS storages, the semiconductor cell area can be further reduced.

Igfet flip-flop having facility for forcing its state

Abstract: A bi-stable flip-flop circuit utilizing insulated gate field effect transistors in a plurality of logic circuits connected to receive a bi-level signal and the inverse thereof on two inputs and to supply an output signal and the inverse thereof on two outputs, the outputs being of a frequency of one-half of the frequency of the input signals. The output signal and the inverse thereof can be forced to a predetermined binary value and the inverse thereof by the application of a state-forcing signal, irrespective of the input signals.

Flip-flop circuit

Abstract: A flip-flop circuit formed of a combination of field effect transistors and in which input signals are controlled in the normal logic system by clock pulses of low level. A quasi-static operation is possible. A clock drive of the field effect transistors for loads is also possible.

500-MHz clock-rate logic LSI

Abstract: The development of 500-MHz clock rate logic LSIs, with a wide operating range, will be discussed, citing a proposed 1-GHz flip-flop operating stably as a master-slave flip flop.

Broken thread monitor circuit - for textile machinery

Abstract: An analogue signal representing the number of operating or stationary spindles of the machine is converted to digital form and this signal is fed into a memory stage and simultaneously to one input of a comparator. A clock circuit gates the read out form the store into a second input of the comparator at regular intervals so that the comparator produces an output pulse immediately a difference appears between the instantaneous value of the digital status signal and the previous sampled value as stored. The same clock circuit resets a flip flop and opens an AND gate in a signal chain from comparator to the indicator which steps on one figure for each thread break indicated by the above difference signal.