Showing papers on "Flip-flop published in 1974"

Test technique for semiconductor memory array

Abstract: Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.

Failure detecting and inhibiting circuit

Abstract: A logic equivalence gate compares signals supplied to and received from an electronic switching circuit to produce an output signal when the switching circuit fails to perform a specified switching operation. A pulse width discriminator rejects noise normally present in the output signal caused by the inherent delay of the switching circuit in normal operation. The noise free output of the pulse width discriminator is applied to a flip flop to provide a stored indication of failure of the switching circuit. The stored signal is also applied to an inhibit gate connected to the input of the switching circuit for preventing further application of input signals to the switching circuit after failure has been detected.

Current switch emitter follower master-slave flip-flop

Abstract: The operating speed of a sequential OR/NOR current switch emitter follower master-slave flip-flop is improved by adding an additional master section or block in order to eliminate input sequential gating circuitry and still accommodate and provide a NAND/AND logic function.

Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

Abstract: A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state when a fault exists is described. Finally, some extensions of the technique are attempted.

Logic circuit including J-K flip flop providing output pulse in respose to longer duration input pulse

Abstract: There is disclosed a logic circuit utilizing a bistable multivibrator and NOR gate digital components to provide an interrupt request signal to a utilization device in response to the leading edge of a longer duration switching signal. The switching signal is applied to the set input of the bistable multivibrator and further to a gate enabled by the set output of the bistable multivibrator being reset. The bistable multivibrator is then set upon command of the utilization device, causing the gate to become disabled. The trailing edge of the switching signal causes the bistable multivibrator to become reset, thereby re-establishing the initial conditions.

Binary universal flip-flop employing complementary insulated gate field effect transistors

Abstract: A universal J-K flip-flop is implemented with insulated gate field effect transistors of both P and N channel types. The transistors are interconnected as a plurality of AND gates and NOR gates, with some transistors serving a dual function in both the master and slave portions of the flip-flop. A provision for direct set and reset of the flip-flop also is included.

Flip-flop element

Abstract: Flip-flop circuits are defined by bipolar elements including multiple emitter transistors, Schottky diodes and multiple emitter Schottky transistors configured to operate with a supply voltage of only 1 volt. The circuits are well adapted for use in devices such as electronic wrist watches when implemented in integrated circuit form wherein current sources are used in place of high value resistors.

Cmos flip flop memory element without crossover, and method of operation

Abstract: A B S T R A C T A static semiconductor storage element includes a flip-flop formed of a pair of complementary field effect transistors which are cross coupled without intersection to form a bistable circuit. One node of the flip-flop is connected to a terminal which is employed for both reading and writing functions. The flip-flop is set or reset by connection of an appropri-ate voltage to the node, and nondestructive read out is carried out by sensing the voltage level of the node.