Showing papers on "Flip-flop published in 1977"

Sense circuit employing complementary field effect transistors

Abstract: A sense circuit suitable for use with semiconductor memory arrays which, in contrast to sense circuits of similar type, exhibits no voltage offset in the latched condition between the input-output (I/O) nodes and the supply lines. The sense circuit includes first and second complementary inverters with inputs connected to first and second I/O nodes, respectively, and with outputs capable of being clamped to one or the other of the two supply lines powering the inverters. Selectively and sequentially enabled cross-coupling transmission gates are connected between the output of each inverter and the input to the other inverter, and selectively enabled biasing transmission gates are connected between the input and output of each inverter. In the operation of the circuit, the two input nodes are first precharged to a predetermined value by enabling the biasing gates. A signal is then applied to one I/O node causing its potential to vary from its quiescent value. Then, the cross-coupling gate connected to the output of the inverter whose input is connected to the one I/O node is first enabled and, subsequently, the other cross-coupling gate is enabled. When the two cross-coupling gates are enabled, the inverters are latched and form a flip flop with the first I/O node clamped to the supply line having the same binary signal and the second I/O node clamped to the other power supply line.

Master-slave flip-flop circuit

Abstract: A logic circuit, which includes master-slave flip-flops, advantageously designed to place both the master and the slave flip-flops in a predetermined logic state so that the logic circuit can be tested in one clock cycle in the same manner as a combinational logic circuit is tested

Presettable dynamic delay flip-flop circuit

Abstract: of the Disclosure A presettable dynamic delay flip-flop circuit including two first and second series-connected ? bit delay circuits, a gate circuit for supplying these delay circuits with a control signal for controlling their operation, and a switching circuit for supplying the second delay circuit with preset data capable of freely presetting the voltage level of an output signal from said flip-flop circuit. The delay circuits and switching circuit are respectively formed of clocked inverters. The flip-flop circuit is formed of a small number of elements and operated at high frequency.

Electronic automatic control for electromagnetic agitators - uses permanent magnet to trigger field plate sensor with flip flop and logic OR:gate

Abstract: The unit for electronic automatic control of electromagnetic agitators (stirrers) in sealed pressure vessels uses a permanent magnet for switching the working current for the magnet winding, the permanent magnet being fixed to alengthwise movable armature within a pressure tight non-magnetic housing The permanent magnet triggers a field plate sensor applied externally to the pressure-tight housing, at the upper and lower dead-centres (TDC and BDC) of the armature stroke or throw The field plate sensor signal is fed via an amplifier to a flip flop and thence via a logic OR-gate to the gate of a thyristor More specif a separate multivibrator circuit is used to set the armature stroke frequency, with variation, independent of the main multivibrator's pulse and automatic drive

Electronic counter for summing pulsed measurement values - operates with sources giving measurement values in different ranges using clock and address generators with coupled astable flip flops

Abstract: An electronic counter for summing measurement values in the form of electrical pulses from two or more sources is designed to operate with sources giving values in different ranges. Each source is associated with a pulse register bistable flip flop with bistable preset counters whose outputs are connected to several AND gates controlling an astable flip flop. A clock generator and address generator are made with coupled astable flip flops. Each pulse register is connected to one input of an associated three input AND gate whose other two inputs are connected to the address and clock pulse generators. Each AND gate output is connected to a multiplier circuit and, via an OR gate, to a common divider circuit. Each multiplier output is connected to the corresponding pulse register reset channel.

Flip-flop with setting and sensing circuitry

Abstract: A flip-flop comprising two, cross-coupled, transistors each having one end of its main conduction path connected to a common current source, and in which switching between states is accomplished by the application of voltages coupled through voltage dropping resistors connected to the other ends of the main conduction paths of the two transistors. The circuitry for applying the switching voltages includes an emitter-coupled logic (ECL) gate comprising a differential amplifier stage containing a pulse forming network for producing a sampling pulse at one output and a clocking signal at another output. The sampling pulse is "AND'ed" with input data signals to set the flip-flop to one binary condition and the clocking signal is used to reset the flip-flop to the other binary condition. Circuitry for sensing the state of the flip-flop includes a differential stage whose inputs are coupled to the control electrodes of the transistors of the flip-flop.

A Clocked Multivalued Flip-Flop

Abstract: A multivalued flip-flop is presented. The implementation of the flip-flop is independent of N (number of logic levels). The output of the flip-flop is stable during clock transitions. Techniques in the design of sequential circuits using this type of multivalued flip-flops are presented.

Flip-flop circuit

Abstract: A flip-flop circuit includes first, second, third and fourth NAND gates each with first and second output terminals. The first output terminal of the first NAND gate C and the first output terminal of the third NAND gate are connected to the input terminals of the second and fourth NAND gates, respectively. The first output terminals of the second and fourth NAND gates are connected to the input terminals of the first and third NAND gates, respectively. The second output terminals of the first and second NAND gates are connected to the input terminals of the third and fourth NAND gates, respectively. The second output terminal of the fourth NAND gate is coupled with the input terminal of the first NAND gate. A first diode is inserted between the input terminals of the first and second NAND gates and second diode is inserted between the third and fourth NAND gates. An input signal is applied to the input terminal of the second NAND gate, and an output signal is taken from the second output terminal of the third NAND gate.

An integrated JK flip-flop circuit

Abstract: An integrated JK flip-flop circuit, which is constructed using an RS flip-flop and four gates, is described. The circuit operation is based on an original concept, which is different from the conventional master-slave principle. Results of a monolithic integration using emitter-coupled logic (ECL) circuits are also given. As compared with the conventional master-slave-type JK flip-flop, which is constructed using ECL, a 40 percent improvement in speed-power product has been obtained.

NRZ to RZ signals conversion for synchronous TDM system - involves using D flip flop and AND gate feedback with clock

Abstract: The converter, for synchronous TDM systems, converts NRZ signals into return-to-zero signals without experiencing the problems of generating two 180 deg.-shifted signals due to component tolerance scatter and temperature effects. An AND- or NAND-gate is connected by its output to the input of the D-flipflop (1). This gate has its first input connected to the output of the D-flipflop and its second input is connected to the NRZ input signal. The clock input of the D-flip flop is connected to a clock signal line (T) carrying clock signals whose frequency is twice that of the repetition rate of the NRZ signal. If an AND-gate is used it is connected to the flip flop inverting output. If a NAND- gate is used it is connected to the non-inverting output.

Flowmeter correction circuit for fluid esp. gas measurements - has output pulses fed to frequency divider and counter and to set input of bistable flip flop

Abstract: The flowmeter correction circuit for measurements on fluids provides automatic compensation for variables such as temp. and pressure so that a true volumetric reading is obtained. Output pulses from the pipeline flowmeter are fed to a frequency divider and counter and to the set input of a bistable flip-flop. At each input pulse, the bistable provides a pulse to open gates connected on the outputs of a temp. sensor, pressure transducer and fixed frequency oscillator. The bistable is reset by the gated and divided output of the temp. sensor. The gated and divided outputs of the pressure sensor and fixed oscillator are passed to a subtraction circuit whose output drives a counter which displays the corrected fluid vol. measurement.

Polyphase MOSFET circuit for pulse duration variations - uses ring counters with decoders connected to RS flip flop controlled by digital signal applied to AND gates

Abstract: The polyphase MOSFET circuit, for varying pulse duration in steps, has step width dependent on clock frequency and max. pulse duration determined by pulse frequency. Input signals are applied via two AND-gates (25, 26) to two ring counters (11, 12) with decoders (13, 14) at their outputs. The decoders are coupled to the inputs of an RS-flip flop (15) whose output forms the circuit's output. Two clock signals (F1, F2) are applied via two AND-gates (19, 20) and an OR-gate (21) to an AND-gate (22) lying between the flip flop's S-input and one decoder output. The digital control signal (17) that alters the pulse duration is applied via a divider (16) to all the AND-gates.

Control circuit for PCM TDM test circuit in telephone - switches from test to hold when busying acknowledgement fails

Abstract: The control circuit, for a test circuit connected to the incoming signalling in a PCM TDM telephone network, has the hold circuit's control signal adopting one state and the test circuit's control signal adopting the other state if the change in the incoming control signal from one condition to the other does not take place within a given time. The circuit has a flip flop comprising cross-coupled NAND-gates connected in a specified way via diodes and resistors to the evaluator, control line and test circuit.

Asymmetric astable flip flop transmission system - transmits two sets of information by pulse width modulation and has voltage control

Abstract: The transmission system transmits two sets of information as pulse width modulated signals using a voltage controlled a stable multivibrator . the information, in the form of two DC voltages, is applied to the base inputs of the multivibrator (3) and each causes a train of pulses to be produced complementary to one another. The multivibrator is asymmetric and has RC circuits with different tone constants to produce output signals of different frequencies. The durantin and intervals of the pulses are determined by the magnitudes of the signal voltages. The receiver contains a first integrator, a sample and hold circuit, for demodulation, an inverter and a second integrator and sample and hold circuit.