Showing papers on "Flip-flop published in 1981"

Flip-flop circuit

Abstract: PURPOSE:To perform high-speed FF operation for a data input of complicate logic with the same number of element and power consumption as usual, by multiplexing master FF and by dispersedly allotting logical processing to even slave FF. CONSTITUTION:Data are retained by two master FFs34 and 35 separately and their out-of-phase outputs are ORed by input gate 31 of slave FF36 to perform conventional DFF operation on the whole. Both FFs34 and 35 are driven with the same clock 23 at the same timing and input gate 31 of FF36 has not an increase in time lag due to an increase in the number of fan-ins neither to eliminate the need for a gate for data input logical operation, improving a maximum operating clock frequncy. Then, high-speed FF operation is performed to a data input of complicate logic with the same number of elements and power consumption as usual.

PLL circuit with a digital phase discriminator

Abstract: A PLL circuit contains a digital phase discriminator which outputs a first signal for controlling the PLL oscillator (VCO) when the input signal arrives during a first phase of the PLL oscillator, and a second control signal when the input signal arrives during a second phase. To determine the phase difference, a first bistable flip flop (FF1) is enabled in the first phase of the oscillator signal, set by the input signal and reset at the end of the first phase. During the second phase of the oscillator signal, a second bistable flip flop (FF3) is enabled which is also switched with the input signal. This triggers a timing element (DL) which outputs pulses of a duration which are equal to that of the second phase of the oscillator signal. PLL circuits are used in devices for reading data from memories with a mechanical drive mechanism.

Hybrid unlatching flip-flop logic element

Abstract: Described is a DC powered flip-flop logic or memory element (i.e., circuit) which comprises two Josephson junction gates J 1 and J 2 which operate individually in the latching mode. In one logic state, the gate J 1 is at V 1 =O while J 2 is at V 2 ≠O. In the other logic state, the roles of the two junctions are reversed. The two junctions are interconnected by a passive network such that the switching of J 2 , say, from V 2 =O to V 2 ≠O induces a current-voltage transient on J 1 which returns it to V 1 =O, and conversely.

Semiconductor integrated circuit possible for logic change

Abstract: PURPOSE:To enable to make easy the change, when the necessity of logic change is taken place, by providing a plurality of flip flop circuits located corresponding to a plurality of additional gates and gates themselves with the semiconductor integrated circuit. CONSTITUTION:The logic operation circuits LG1, LG2, LG3 are added with additional gates ELG1,ELG2 and the control flip flops FF1, FF2 are located corresponding to the additional gates. As to the flip flops FF1, FF2, for example, the specified gate is activated by suitable control of set or reset by using the computer console, and the application of additional logic to the external control terminal EXT1 enables new operations, allowing to obtain the new operation output at the logic circuit output.

Synchronizing circuit for asynchronous signal

Abstract: PURPOSE:To decrease the hardware and to reduce the synchronizing time, by latching and holding the asynchronizing signal at the opposing edge as the operating edge of clock fed to flip flop. CONSTITUTION:The set condition of a latch consisting of an NAND gate 4 and an NAND gate 3 is taken as the front ridge of the clock 102 where a signal 101 of data input terminal DATA is not given directly to the data input D of a D type flip flop 1, but fed to the clock terminal CLK, that is, the AND condition of an inverting signal 108 of delay signals of the clock 102 and the clock 102 itself, and the output 106 of an AND gate 105 driven with the clock 102 fed from the clock terminal CLK is taken as hold condition, and the output 105 of this latch is taken as the data input D of a D type flip flop 1.

Delay type flip-flop

Abstract: In a master-slave delay type flip-flop, a first transistor transfers the data at the D input to an inverter stage when the clock signal goes low. When the clock signal again goes high, the inverter data is transferred to a second inverter stage which forms the flip-flop Q output. Feedback means have provided for latching the inputs to both the first and second inverter stages. An inverting transistor in one of the feedback paths forms the Q output of the flip-flop. Additional embodiments of the D-type flip-flop circuit include both asynchronous set and reset features.

Ignition timing controller for ignitor of internal combustion engine

Abstract: PURPOSE:To improve response performance to rotary speeds and to easily obtain dual vacuum advance characteristics by connecting a series circuit in parallel, which consists of a bypass switch and a current limit element to the output terminals of a signal composite circuit which outputs ignition timing signals. CONSTITUTION:An ignition timing controller 4 is provided with the first, second and third signal generators 5, 6 and 7 which output the first, the second and the third signals respectively at the specified rotary angle of the crank shaft of an engine. The first and the second signals enter a signal composite circuit 8 where they are composed. The first and the third signals enter a flip flop circuit 11 through wave shaping circuits 9 and 10. When the flip flop circuit 11 is set, the bypass switch 13 is turned on and bypasses a part of outputs of the signal composite circuit 8 from an ignition control circuit 3. The outputs of the signal composite circuit 3 enter the ignition control circuit 3 as a signal which determines ignition timing.

Battery test circuit for electronic flash unit - has timing circuit and D-type flip=flop display driver circuit

Abstract: The arrangement is for the measurement of the state of charge of a battery used to operate a Voltage converter and storage capacitor circuit for an electronic flash unit, esp. one built into a camera, gives a reliable automatic indication shortly after the circuit is switched on. The time taken for the storage capacitor (7) to charge up to a defined voltage force is compared with a reference time from a clock circuit (2). An electrical indicator (10) is controlled according to the result of the comparison. The time circuit (2) is triggered when the main switch (1) is turned on. After a reference time it triggers a bistable (5) when the latter voltage has been attained. The bistable, a D-type flip-flop, drives the indicator. It can also control the camera shutter release.

Pulse frequency divider - has variable frequency and ion jitter level achieved using multiplier and flip=flop dividing chain

Abstract: The frequency divider has a pulse rate multiplier coupled at the output to a divider comprising a chain of flipflops. Whenever the selected frequency of the output pulse sequence drops below a power of two, a flip flop stage is disconnected from the multiplier (2) and a flip flop stage is connected into the flip flop chain (4). Logic gates are used to switch out stages in the multiplier. Switch-out signals for stages in the multiplier are passed to the gates and simultaneously cause flip flop stages to be switched into the flip flop chain. The circuit reduces jitter at low output frequencies.

D type flip-flop

Abstract: PURPOSE:To obtain a D type FF without malfunction even with the connection of multistage, by providing a transfer gate at the input and output side of an inverter having a feedback path CONSTITUTION:When a control signal from a control terminal 22 is at H level, the 1st transfer gate 24 is conductive and the input signal is fed to an inverter 27 When the control signal is at L level, the gate 24 is nonconductive and the 2nd and 3rd transfer gates 25, 26 are conductive Thus, the feedback path consisting of an inverter 28 and a gate 25 is conductive and the input signal is stored Simultaneously, new data are transferred to an inverter 29 via a gate 26 Thus, since this circuit has the same function as a master slave FF, no malfunction produces even with multistage connection

Flip-flop circuit of set and reset type

Abstract: PURPOSE:To increase the reliability of FF circuit, by avoiding the malfunction when noise is mixed to the input signal, through the input of the output signal of auxiliary FF of reset type FF on the way of the logic circuit of main FF and compulsive reset of FF with the reset signal. CONSTITUTION:R-S type FF consists of master FF10 and slave FF20, and FF10 consists of composite inversion circuits 11, 12 consisting of AND gates 1, 2, NOR gates 3, 4 and AND gates 32, 31, and the output signal QM is fed to the gates 31, 32. Further, FF20 inputting the signal QM consists of OR gates 5, 6 and NAND gates 7, 8. Further, the output signals Qs, -Qs of FF20 are fed to the gates 32, 31 of the circuits 11, 12 to compulsively reset FF with the reset signal R, allowing to prevent the malfunction when noise is mixed to the input signal and to increase the reliability of FF.

J-k flip-flop circuit

Abstract: PURPOSE:To prevent the malfunction when noise is mixed in the input signal and to increase the reliability of FF, by negative feedback of the output signal of J-KFF to the input side and supplying it on the way of composite logic circuit of FF. CONSTITUTION:J-KFF circuit is constituted with the master FF10 and slave FF20, and FF10 consists of composite logic circuits 3, 6, consisting respectively of AND gates 1, 4, NR gates 2, 5, and AND gates 31, 32, and the output signals -QM, QM of FF10 are mutually fed to the gates 31, 32. Further, FF20 consists of composite inversion logic circuits 13, 16 consisting of OR gates 11, 14 and NAND gates 12, 15. The output signals QS and -QS of the gates 12, 15 of the circuits 13, 16 are respectively negative-fed-back to the input of FF10 and fed to the gates 31, 32 on the way of the circuits 3, 6, to prevent the malfunction when the noise is mixed to the input signal, allowing to increase the reliability of the output signals Q, Q' of FF.

Digital frequency meter

Abstract: FIELD: measurement.SUBSTANCE: invention relates to measurement equipment and can be used in gyroscopes - magnetrons, radio engineering, in microcontrollers and other devices, where high-frequency precision measurement of signals to tens of gigahertz and their small deviations from nominal values, as well as very short time intervals is required. Digital frequency meter, which includes an input signal receiving port, a high-stable count pulse reception port, three groups of counters with a meter output register, triggers connected to the synchronization and control circuit, in the form of an additional flip-flop for determining a measurement interval and a flip flop of two channels, made in the form of two groups of reversible counters from the high-order and low-order bits, also two multiplexers of high and low order, designed to change display of output information from channels, logic elements unit designed to control generation of counting interval, determination of frequency difference of input and reference signals and switching channels and counting symbols of difference of these frequencies, memory register of whole part of input signal, as well as a fractional part corrector in the form of its divider into a measured frequency mantissa, made on the basis of a programmable integral logic structure chip, characterized by that the digital frequency meter includes a generator of an expanded window for counting frequency pulses of the order ~ ƒƒwith ADC with output of number-pulse or frequency-pulse type (FPT), which input is voltage level integrator-integrator proportional to duration of accumulated difference phase between reference and measured frequencies, also comprising stretching pulse generator with time-setting capacitance, inverter with ADC control input and to control device, analogue key in integrator feedback circuit for control thereof, operating capacitance and resistor, dividers at inputs of operational resistor and non-inverting input with diodes in lower arms, separating capacitance between input of former and integrator input, at that, outputs of the first multi-input circuit "and - not" are connected to the corresponding inputs of the logical elements unit, outputs of flip-flop switching of the first channel to the second, outputs of the generator of the expanded window of counting pulses, with outputs of the block of logic elements are connected control inputs of n input counters, register control inputs for storing the integer value of the input signal, inputs of the low-order counters of the first and second channels, wherein outputs of the two high-bit counters are connected to inputs of the high-output switching multiplexer, and outputs of two low-rank digits are connected to low-output switch switching multiplexer inputs, register outputs and multiplexer unit are connected to corresponding chips of programmable logic integral structure microcircuit, first output of which is difference frequency between input and reference signals, and second output thereof and digital frequency meter as a whole - an integer number of input pulses of input signal over measurement period.EFFECT: invention is expected to be used in orientation and navigation systems on mobile objects - aircrafts, ships and others, in the form of sensors, which require continuous operation and sufficient frequency of information output.1 cl, 4 dwg

Phase shift circuit

Abstract: PURPOSE:To reduce the power consumption of a phase shift circuit and to lower the frequency of input signal, by phase-shifting the input signals being shifted in the phase by 180 deg each other at the phase shift circuit, with the output obtained by switching said signals with the control signal by 90 deg toward the specified direction CONSTITUTION:An input signal 5 is frequency-divided into two at flip flop FF4, and Q, Q' outputs are respectively fed to gates S5, S6 The Q, Q' outputs when the control signal 6 is frequency-divided by 4 at flip flops FF7, FF8 are fed to the control input terminal of the gates Accordingly, the signal fed to the input terminal D of the flip flop FF5 is either one signal of the Q, Q' outputs of the flip flop FF4, and it is switched from one to another when the outputs Q, Q' of flip flop FF7 are switched Accordingly, at this time point, 90 deg phase shift is made to the specified direction Thus, since the frequency of input signal is two times in comparison with 4 times the frequency of output signal which is conventional, the signal processing is made easy and the power consumption is lowered

Digital phase comparator controlling contents of memory - has input and output counters connected by gate and to flip=flop and gate system

Abstract: The digital phase comparator has an input counter connected to a memory, and the outputs of the memory electrically connected to the inputs of a selector circuit. Connected to the selector circuit is an output counter and this is connected to the input counter by a NAND gate. The input data is read at a lower frequency than that of the output data. The output of the gate is fed to a flip-flop followed by a timing signal controlled flip-flop. The first flip-flop is also connected to a second NAND gate so that it is return operated at the same time as a stuffing bit is entered.

State detector for electric discharge machining

Abstract: PURPOSE:To facilitate the determination of machining conditions and to attain stable electric discharge machining by providing a detecting circuit for detecting the state of discharge and a merging circuit capable of merging the output signals of the detecting circuit and of detecting the duration of the discharge state. CONSTITUTION:Set voltages E1, E2 and E3 are set by level setting circuits 6, 7 and 8. The discharge state is detected and dicriminated by timing pulses T1, T2 and T3. In normal discharge detection, the output waveform signals of the first comparator-amplifier 9 and the second comparator-amplifier 10 are applied to an AND gate circuit 12 which in turn provides an output waveform signal. The output waveform signal of an AND gate circuit 13 is dependent on the output signal and the timing pulse T1 of the third comparator-amplifier 11 set by the third level setting circuit 8. The output waveform signal of an AND gate circuit 15 is determined by three inputs to the AND gate circuit 15, namely, the signal and the timing pulse T2 of a flip flop 14 and the waveform of the AND gate circuit 12. The output waveform signal of the AND gate circuit 15 represents the normal discharge discriminating signal.