Showing papers on "Flip-flop published in 1982"

100 GHz Binary counter based on DC SQUID's

Abstract: A binary counter using bistable dc SQUID's as flip flop circuits is demonstrated. All of the functions: LOAD, COUNT, STORE, READ, and CLEAR can be performed. The use of single flux quantum logic results in high sensitivity (10-18J input pulse energy), high speed (100 GHz count rate) and low power (10-7W at 100 GHz count rate).

Flip-flop resolving time test circuit

Abstract: Integrated circuit flip-flop resolving time parameters, required for calculation of synchronizer performance and reliability, are measured by wafer probing, without the need for dicing or bonding, by incorporation of test structures on an IC along with the flip-flop to be measured. The circuit has five digital inputs, five digital outputs, including one for frequency measurements, and two analog inputs plus power and ground connections. Several delays that are fabricated as part of the test circuit, including a voltage controlled delay with a few picosecond resolution, are calibrated as part of the test procedure by grating them into and out of the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted, from the period of the ring oscillator with the delay included. A frequency divider is fabricated as part of the test structure to reduce the output of the ring oscillator to less than 200 kHz so no high-frequency inputs of outputs from the IC are required.

Non-volatile flip-flop with a dynamic resetting

Abstract: A flip-flop further comprising two branches with MNOS elements serially connected with P channel MOS transistors for permitting a non-volatile storing of the informations comprised in the flip-flop at a chosen storing time. The memorization of the state of the flip-flop can be made in a single cycle by acting on the control signal applied to the gate of the P channel transistors and on the supply voltage of the device. In the same way, the resetting can be made in a single cycle.

High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gates

Abstract: A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.

Flip-flop circuit

Abstract: A flip-flop circuit of set-reset type comprising complementary MOS transistors. The flip-flop circuit comprises a first CMOS NOR circuit (10) to which set signal (S) is applied, and a second CMOS NOR circuit (12) having same arrangement as the first CMOS NOR circuit and to which reset signal (R) is applied. Set signal (S) is the logical product signal (φ S .f S ) of first set signal (s s ) and second set signal (f s ). Reset signal (R) is the logical product signal (φ R .f R ) of first reset signal (φ R ) and second reset signal (fR). Neither of first set and reset signals (φ S , φ R ) becomes logic "1" simultaneously. Second set and reset signals (f s , f R ) are kept either unchanged during the time period when first set and reset signals (φ S , φ R ) are logic "1" or become logic "1" only during the time period when first set and reset signals (φ S , φ R ) are logic "1". The first NOR circuit (10) comprises first and second transistors (Tr5, Tr4) of first conductivity type connected in series between first power supply terminal and third transistor (Tr2), third and fourth transistors (Tr2, Tr1) of second conductivity type, and a fifth transistor (Tr3) of second conductivity type connected between the node of second and third transistors (Tr4, Tr2) and the second power supply terminal. First set signal (φ S ) is applied to gates of first and fourth transistors and second set signal (f s ) to the gate of third transistor. The second transistor (Tr4) is gate-connected to the fifth transistor (Tr3).

Power supply circuit for flip-flop memory

Abstract: A memory device is disclosed which is automatically and stably set to a predetermined logic state upon the application of power thereto. The memory device comprises a flip-flop having first and second cross-connection points, a state setting transistor coupled between the second cross-connection point and a reference voltage terminal, a voltage detection circuit for detecting the value of a power supply voltage, and a reset circuit responsive to an output signal of the detection circuit for controlling the state setting transistor.

Digital regenerator for alternate mark inversion coded signals - uses discriminators and D=flip=flop(s) with verification of output signals

Abstract: The regenerator has a pair of discriminators (D1,D2) coupled to the signal input (SE), each using a difference amplifier with the switching thresholds corresp to the digital signal thesholds Each discriminator (D1,D2) is coupled to a respective D-type flip-flop (DF1,DF2) The two outputs (Q,Q) of each flip-flop (DF1,DF2) are coupled to the resetting or setting inputs (R,S) of a RS flip-flop (RSFF) and to a further respective D-type flip-flop (DF3,DF4) and a NOR gate (NOR1,NOR2) respectively The other outputs of the NOR gates (NOR1,NOR2) are coupled to the inverted outputs (Q) of the second pair of D-type flip-flops (DF3,DF4), their outputs coupled to an evaluation circuit (AS) for error indication The regenerator incorporates code verification of the regenerated signals

Picture receiver for measurement

Abstract: PURPOSE:To eliminate the flicker of display on a screen, by synchronizing the start and the end of a marker with a horizontal synchronizing signal CONSTITUTION:The vertical synchronizing signal from a terminal X1 in inputted to monostable multivibrators 2 and 3 through a buffer 1 The flyback pulse from a terminal X2 is inputted to a D type flip flop 4 as a clock pulse through a buffer 5 The output of the monostable multivibrator 3 is supplied to a video circuit as a blanking signal Y1 and is synthesized with a pulse of the horizontal period by a waveform synthesizing circuit consisting of amplifiers A1 and A2 and diodes D1 and D2 The output of the amplifier A2 is supplied as an oscillation start pulse of an oscillator 6 The output of the oscillating circuit 6 is applied to a buffer circuit through a differentiating circuit and a waveform shaping circuit 7 and is further supplied to a color circuit

Simultaneous counter in positron ct system

Abstract: PURPOSE:To remove false data correctly when the simultaneous events occur in detectors in a group, by detecting said simultaneous events by a logic circuit, and inhibiting the output of the timing signals from the detectors in the group. CONSTITUTION:The outputs of four detectors 10-13 in the same group 1 are inputted into an address encoder 3, an OR gate 5, and a mutiple simultaneous events checking circuit 2. A flip flop 6 receives the output of the OR gate 5 at a clock input CK and the output of the check circuit 2 at a data input DI. The address encoder 3 receives four inputs which are the output signals A-D, and forms the addresses corresponding to said inputs. A latch circuit 4 latches the output addresses from addres encoder 3. A reset circuit 7 resets the flip flop 6. The check circuit 2 is constituted by exclusive NOR gates 20 and 22, OR gates 21, 23, and 26, and NOR gates 24 and 25.

Master and slave flip-flop

Abstract: PURPOSE:To reduce power consumption by putting a master-side latch circuit in operation with a strobe signal only in reading operation for an input signal. CONSTITUTION:When a flip-flop should be put in operation, a strobe ST signal C is supplied at faster timing than that of a clock signal CLa. The output signal (d) of a gate G19 is the output of NAND between the ST signal and an input signal INb and supplied to a gate G12. The output of a gate G11 is generated only until the ST signal C is inputted, the input signal INb is at a level H and the clock signal CLa is inputted, and from the gate G12, the ST signal C is inputted to generate an output only until the input signal INb is at a level L and the clock signal CLa is inputted. The outputs of gates G11 and G12 are read into the gates G13 and G14 with the ST signal C to be latched.

Defect checking device

Abstract: PURPOSE:To use effectively an earlier bit output in the scanning direction of an image sensor, by holding a photo gate voltage which is applied to the image sensor, in a value higher than an output gate voltage. CONSTITUTION:When a light leaked from a defective parts is inputted to image sensors 1 and 2, a positive hole generated in a photo gate is transferred to analogue shift registers 112 and 223 and is taken out from output gates 113 and 224. Outputs of flip flop circuits 7 and 8 to which these outputs are inputted through discriminators 3 and 4 are inputted together with the output of a clock pulse generator 9 to counters 12 and 13 through gate circuits 11 and 10, and the width of the defective part is obtained by an adder 14. Meanwhile, voltage distributing circuits 15 and 16 can adjust voltage values to set photo gate voltages of image sensors 1 and 2 to values higher than output voltages. Thus, a blooming phenomenon is generated in the trailing edge in the scanning direction of the discrimination output.

Flip-flop circuit

Abstract: PURPOSE:To increase the degree of integration through addition of preset function with less number of elements, by constituting a gate consisting of inverters of master latch and slave latch with a tri-state inverter. CONSTITUTION:A tri-state inverter 11 is used for a master latch 1 constituting a master slave flip-flop circuit and a gate of a slave latch 2. The tri-state inverter 11 turns off at load timing and the tri-state inverter 13 turns on, allowing to ?make independent of the phase of clock.

Edge trigger t-flip-flop

Abstract: PURPOSE:To obtain an edge trigger T-flip-flop which obtain differentiated outputs, by cross-coupling coincidence gate pairs, each of which is composed of a pair of NAND gates, with each other CONSTITUTION:The 1st NAND gate pair 100 is constituted by cross-coupling the input and output terminals of a 2-input NAND gate 1 and a 4-input NAND gate 2 The 2nd NAND gate pair 200 is constituted by cross-coupling the input and output terminals of a 5-input NAND gate 3 and a 4-input NAND gate 4 The 3rd NAND gate pair 300 is constituted by cross coupling the input and output terminals of a 2-input NAND gate 5 and a 3-input NAND gate 6 Each NAND gate pair is cross-coupled as shown in the figure and a trigger signal input T and reset signal input R are connected to the pairs In this way, an FF which can obtain a differentiated output P in addition to the Q and Q output is constituted

Flip-flop circuit and counter circuit using it

Abstract: PURPOSE:To prevent malfunction due to racing by providing a singal delay means to a positive feedback loop which constitutes an FF circuit. CONSTITUTION:An FF circuit consists of an inverter circuit IN1 which receives a write signal in synchronizing with clock pulses phi, an inverter circuit IN2 which receives the output signal of the circuit IN1, an inverter circuit IN3 which receives the output signal of the circuit IN2 synchronizing with the inverted signal phi' of the pulses phi and then supplies its output signal to the input terminal of the circuit IN2, and a delay circuit D inserted between the circuits IN2 and IN3. In this FF circuit, when the wirting of the signal in performed synchronizing with the pulses phi and holding operation synchronizing with the pulses phi' are changed over to each other, the undefined logical level transition time T1 of the circuits IN1 and IN3 is made shorter than the signal transmission delay time T2' of a positive feedback loop by the circuit. Therefore, malfunction due to racing is prevented.

Flip-flop circuit

Abstract: PURPOSE:To reduce the number of elements to be used, by controlling differential circuits by a common control source in a flip-flop circuit consisting of two bistable circuits which have two differential circuits respectively. CONSTITUTION:Emitters of transistors TRs Q23 and Q24 of a master flip-flop 13 and TRs Q25 and Q26 of a slave flip-flop 14 are connected commonly and are connected to the collector of a multiemitter TR Q29. Emitters of TRs Q21 and Q22 of the master flip-flop 13 and TRs Q27 and Q28 of the slave flip-flop 14 are connected in common and are connected to collectors of TRs Q30 and Q31, and emitters of TRs Q30 and Q31 are connected to the collector of a TR Q32, which is a current source, together with the emitter of a TR Q29.

Retiming circuit for high speed data transmission - in which pulse edges are separated and recombined by flip=flop action to maintain transmission in giga-bit-per-second range

Abstract: The object of the circuit is to provide a retiming system for data transmission in the GBit/sec range for non-return to zero (NRZ) signals. At lower frequencies, a D-type flip-flop is used for this purpose, but due to feedback delays this is limited to operation at about 600MHz. The circuit is in fact a reset-set flip-flop which has the attributes of a D-type flip-flop. The NRZ signal is sampled at its bit rate in a three transistor circuit (T1,T2,T3). The signal is applied to one base (1), the bit rate pulse to another (2) and a reference voltage to the third (T2). The result is a series of return to zero (RZ) pulses of one polarity which are then also inverted in a pnp-transistor cascade (T4,T5). Both polarities arrive at a summing junction (S) via time delays (t1,t2) and damping elements (D1,D2). The summed bipolar signal is applied to a Schmitt trigger circuit (T6,T7) acting as a differential amplifier with feedback, at whose output (3) the NRZ signal is replicated in cleaned up form. The feedback delay can be adjusted by a capacitor (C1). The choice of transistor type assists in preventing internal oscillations, and the almost complete absence of internal feedback loops allows operation at the required frequency.

Indicator for abnormality in signal transmission

Abstract: PURPOSE:To continue indication of an abnormality until contents of a storage device are reset by a reset signal from the external, by inputting a signal detecting an abnormal state in the storage device when the abnormal state is detected, and indicating contents of the storage device. CONSTITUTION:The absence of a pulse input in a prescribed time is regarded as an abnormality, and a voltage of logical L is outputted from a signal monitor part 4 to an abnormality detection output 30a. Since the abnormality detection output 30a is used as the set input of an SR flip flop 6, the flip flop 6 is set, and the signal of the output terminal Q' becomes logic L, and a lamp 5 is lit. Hereafter, the logic of the terminal Q' is held in the logic L independently of the logic of the abnormality detection output 30a. When the operator applies a reset signal to the reset terminal of the flip flop 6 from a conductor 40 after finding the occurrence of the abnormal state to perform a required processing, the logic of the terminal Q' becomes H, and the lamp 5 is extinguished.

Phase correcting circuit

Abstract: PURPOSE:To simplify the constitution, by increasing or reducing the number of frequency dividing pulses in accordance with the phase difference between a data signal RD and a timing signal RT and by generating increasing and reducing pulses by two D type flip flops (D-FF) and one J-K flip flop (J-KFF). CONSTITUTION:The output of a phase comparing circuit at the time when the phase of RD advances more than that of RT is applied to a terminal 14, and the output of the phase comparing circujit at the time when the phase of RD lags more than that of RT is applied to a terminal 15. Signals of terminals 14 and 15 stored in D-FFs 2A and 2B are transferred to a J-KFF 2C by the clock pulse inputted to a terminal 16. The output of the J-KFF 2C is gated in gate circuits 2D and 2E by the clock pulse. Outputs of gate circuits 2D and 2E are used as reset timing of D-FFs 2A and 2B. The number of frequency dividing pulses is increased by one in an outut 17 when the signal is applied to the terminal 14, and the number of frequency dividing pulses is decreased by one in the output 17 when the signal is applied to the terminal 15.

Digitally-controlled semiconductor circuit - has flip=flop with both outputs connected to one input of logic gate, whose output is coupled to extra input of flip=flop

Abstract: The circuit comprises at least one bistable flip- flop. Both signal outputs (Q,Q1) of the flip-flop (G1, G2) are connected to an input of a logic gate (G3). The gate signal output is fed back to an additional signal input of the flip-flop, possibly using additional switching elements. Pref. the logic gate is so designed as to respond to the mestable operating condition of the flip- flop. The outputs of the bistable flip-flop may be formed by outputs of a pair of cross-coupled NOR-gates, while the feedback operating logic gate may be of the AND-type. Alternatively, the outputs are formed by cross-coupled NAND-gages, while the feedback gate may be of the OR-type. The output of the logic gage may be connected to the additional signal input of the flip-flop via an amplifier circuit in the form of a push-pull stage.

Subtraction counter circuit

Abstract: PURPOSE:To simplify the circuit configuration of the titled circuit, by making an arrangement that, among two gate circuits which are inverted against each other by the output of a flip flop, one gate circuit outputs input pulses and the another gate circuit outputs the signal from a counter. CONSTITUTION:When a start signal St is inputted into an AND circuit 11, an input pulse to be subtracted CL inputted into an input terminal at the other side is outputted, and the AND of the pulse CL and the Q-output of a flip flop 18 is obtained at another AND circuit 12 and an output pulse signal C'L is inputted into counters 13 and 14. By obtaining the AND of the output of the counters 13 and 14 and the output from setters 15 and 16 and by obtaining the AND of the output of the flip flop 18, into which the logical value of the above mentioned AND is inputted, and the input pulse CL, a pulse number CO in which a set value is subtracted can be obtained.