Showing papers on "Flip-flop published in 1985"

Configurable logic element

Abstract: A configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip flop with or without set and reset inputs, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output signals from among the output signals of the combinational logic element and the storage circuit.

Output circuit for a programmable logic array

Abstract: An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

Test/master/slave triple latch flip-flop

Abstract: A shift register stage (20) for LSI and VLSI circuits is disclosed and includes a first latching circuit (21) responsive to a data input and for providing a first data output; control circuitry (23) responsive to the first data output and to a parallel data input for providing as a controlled data output a replica of the first data output or a replica of the parallel data input as a function of a control signal; a second latching circuit (25) responsive to the controlled data output and for providing a second data output; and a third latching circuit (27) responsive to the second data output and for providing a third data output. Also disclosed is a shift register (30) for LSI and VLSI circuits which advantageously utilizes the foregoing shift register stage of the invention and which provides for AC or delay testing of an integrated circuit which includes two of such shift registers (30, 60) and a logic network (50) interposed therebetween.

Master-slave type flip-flop circuits

Abstract: In a master-slave type flip-flop circuit, a plurality of bipolar type transistors are used for master and slave flip-flop circuits, and transistors are connected such that glitch noise can be prevented under all input conditions.

Flip-flop circuit

Abstract: PURPOSE:To operate a flip-flop circuit with one transfer clock by providing a data storage circuit and a switch circuit consisting of an MOSFET in the master side as well as the slave side. CONSTITUTION:A signal M of a data storage circuit 6 in the master side turns on a switch circuit 8 and goes to the low level forcibly if an anti-phase input data signal DIN is in the high level and a transfer clock signal CL1 is in the high level. Similarly, a switch circuit 7 is turned off, and the anti-phase signal M goes to the high level. If the input data signal DIN is in the high level, the switch circuit 7 is turned on, and the anti-phase signal M goes to the low level forcibly, and the switch circuit 8 is turned off, and the signal M goes to the high level. Thus, input data DIN can be transferred to the data storage circuit 6 in the master side when the clock signal CL1 is in the high level. Similarly, stored data in the master side can be transferred to a data storage circuit 9 in the slave side when a transfer clock signal CL2 is in the low level. Consequently, this flip-flop circuit is operated with one transfer clock.

Optical delay type flipflop and shift register using it

Abstract: An optical D flipflop comprising a 2×1 optical switch and a optical bistable element. The flipflop has a first input end adapted to receive optical digital data, a second input end adapted to receive a biasing optical signal and at least one output end for emitting a light beam comprising the bias signal or optical information pulses, depending upon the state of a clock signal applied to the signal flip flop switch. The flip flops, when connected in cascade through light branching circuits, act as a shift register.

Interference free D-type flip-flop

Abstract: An electronic D-type flipflop includes two storage elements and two transmission gates wherein each gate includes only one MOS transistor. In the first gate the MOS transistor is of a first conductivity type and it is of a second conductivity type in the second gate. The MOS transistors each receive the same clock signal at their gate electrode. Because it is not necessary to form an inverted clock signal, problems due to phase differences between the clock signal and its inverse are precluded. Each of the storage cells includes a pair of inverters which are coupled end-around. The transmission characteristic of the forward inverting circuit is adapted in such a way that it compensates for the voltage drop across the preceding transmission gate. Only a small substrate surface area will be required when the flipflop is used in an integrated circuit.

Flip-flop circuit with built-in enable function

Abstract: A flip-flop with a built-in enable function realized by the addition of two transistors between the trigger circuit and the output nodes of the flip-flop. This embodiment of the enable function causes no increase in power dissipation and may be used in any type of flip-flop.

Flip-flop circuit

Abstract: PURPOSE:To obtain a master slave FF having scan-in/scan-out function with excellent AC characteristic by forming the circuit with three latch circuits. CONSTITUTION:A latch circuit L1 latches a data input D with a clock C and a scan-in input with a clock A. Then a latch circuit L2 latches an output of the latch circuit L1 by using a clock C or C'. Moreover, a latch circuit L3 latches an output of the latch circuit L1 by using a clock B and its output is used as a scan-out output SO. The latch circuit L1 acts like a master section and the latch circuit L2 functions as a slave section at the system operation, and the latch circuit L1 acts like the master section and the latch circuit L3 functions as the slave function at the scan operation. Thus, the master slave FF circuit of master slave type having the scan-in/scan-out function with excellent AC characteristic is obtained.

Master slave flip-flop circuit

Abstract: PURPOSE:To reduce the number of circuit elements and to decrease the propagation delay time of leading and trailing of a pulse by connecting an FET in series with each input of a master slave FF and giving a clock signal to a gate of each FET. CONSTITUTION:When a clock signal CLK is at level 1, FETs 10, 11 are in conductive state and the level of input signals D, D' is inverted by NOR circuits 3, 4 of a master FF at the trailing point of the level 1 of the signal CLK so as to keep output signals Vout', Vout. The signal CLK is inverted by an NOT circuit 14 at the same time to make FETs 12, 13 nonconductive thereby allowing an output signal of the NOR circuits 3, 4 not to be fed to NOR circuits 7, 8 of a slave FF. When the signal CLK goes to level 0, the FETs 10, 11 are nonconductive and FETs 12, 13 are conductive, the signals Vout', Vout are fed to the circuits 7, 8, which output inverted signals Q, Q'.

Construction of up‐down‐type and shift‐register‐type counters using ternary flip‐flop circuits

Abstract: Construction methods for ternary logic circuits and ternary tri-stable flip-flops, using ternary basic operational circuits composed only of CMOS-ICs have been reported. This paper discusses the construction methods for ternary sequential circuits, such as ternary counters, using those ternary logic circuits and ternary tri-stable flip-flops. Among various types of ternary tri-stable flip-flops, this paper uses two-stage ternary up, down and up-down type JK flip-flops. As the logical-type ternary counters, up, down and up-down type divide-by-10 counters are realized. Considering then, the constructions of divide-by-2 to 9 counters, the input equations for the ternary up- and down-type JK flip-flops are determined. The feedback-type ternary divide-by-8 counter is also discussed. As the ternary shift-register type counters, ternary ring counter, ternary Johnson counter, clockwise and counter-clockwise cycling counters are realized.

Pseudo static flip-flop

Abstract: PURPOSE:To decrease the power consumption at stand-by state by constituting a latch circuit for an output side only of a clocked inverter turned off at the stand-by state in a flip-flop using the clocked inverter. CONSTITUTION:The latch circuit is constituted by an inverter 36 and an inverter 38 controlled with a control signal CNTL and provided to an output side of the clocked inverter 35 turned off at the stand-by state in a CMOS dynamic D flip- flop comprising the clocked inverters 32, 25 and the inverters 32, 36. The inverter 38 is turned off at the operating state and the FF acts like the dynamic type FF and the inverter 38 is turned on at the stand-by state and the FF latches a signal. Since the input potential of the inverter 36 at the stand-by state does not reach the intermediate level, no through-current flows.

Master slave type flip-flop circuit

Abstract: PURPOSE:To fetch accurate data even if the determined time of a data signal is delayed behind that of a conventional circuit by using three kinds of clock signal having time difference. CONSTITUTION:The 2nd clock signal CLK' is inputted to a delay circuit 3 to obtain the 3rd clock signal 302, which is supplied as a strobe signal to the 2nd latch circuit 1. The 3rd clock signal 3-2 is therefore delayed a little bit behind the 2nd clock signal CLK', so the data signal DATA may arrive at a terminal 1-3 while delayed to the extent.

Optical master and slave d flip-flop

Abstract: PURPOSE:To store the data optical signal in the form of the binary output light quantity with the clock optical signal by writing the information accordant with the data optical signal into an optical bistable element at the logical level of one side of the clock optical signal and supplying the bias light needed for said bistable element to hold the information at the logical level of the other side of the clock optical signal. CONSTITUTION:An optical circuit 111 writes the data optical signal D applied to the incident terminal of an optical branch circuit 100 to an optical bistable element 106 when the clock optical signal T is set at a logical level ''1'' and supplies the bias light necessary to hold the written information to the element 106 when the signal T is set at a logical level ''0''. In the same way, an optical circuit 112 writes the output optical signal of the element 106 to an optical bistable element 110 when the signal T is set at a logical level ''0'' and supplies the bias light needed to hold the written information to the element 110.

Control circuit for heat generating head

Abstract: PURPOSE:To reduce the power source capacity of a heat generating head by dividing the heat generating head into two groups, right and left, so as to energize and cool them alternately. CONSTITUTION:As an oscillator 7 generates a pulse OSC, an output pulse is applied to a controller 1 with a flip flop 8 from an AND gate A1. The controller 1 outputs a printing data PRD for one line. With the rising of the subsequent A1 pulse, a latch pulse signal La is outputted from the controller to latch the printing data PRD in latch circuits 9a and 9b. At the same time, the controller 1 outputs an print proceding signal PRC to AND gates A2 and B2. As a result, the heat generating element group 6a provides a heating cycle at the first half of the printing operation and a cooling cycle in the latter half thereof.

Loop setting system for folding test of repeater

Abstract: PURPOSE:To generate a folding loop with resupply of power to a repeater even if there is not a signal break detection signal of a down repeater, by providing a power supply detecting part consisting of a rise voltage detector, an RS flip flop circuit, and an AND gate circuit of negative logic. CONSTITUTION:When power is supplied again to a repeating installation, a power source voltage rise detector 41 detects a certain rise voltage to generate a pulse, and a pulse (a) (in the high level for a negative logic input) is supplied to a terminal S of an RSFF42. Since a state (c) of a reset terminal R bar of the RSFF42 is in the low level, a state (d) of a terminal Q bar of the output is in the high level. As the result, an output (e) of an AND gate circuit 43 of negative logic is in the high level no matter whether an output (b) of a signal break detecting circuit OD of a down repeater 20 is in the high level to indicate signal break or in the low level to indicate signal existence. This output (e) is inverted in a monitor control circuit 30 and is applied to a gate A. Since a main signal is outputted to the gate A from a terminal Q of a discriminating part DEC in an up repeater 10, the main signal is inverted and is outputted to the output of the gate A. Meanwhile, the high level of the output (e) stops passage of a down main signal in a gate C.

Semiconductor integrated circuit apparatus

Abstract: PURPOSE:To achieve an AC-oriented characteristic test at a high accuracy with a simple circuit by incorporating a plurality of edge trigger type latch circuits and a measuring circuit comprising a multiplexer. CONSTITUTION:An internal logic circuit LOG receives signals from external input terminals IN1-INm to perform a information processing operation as dictated by the logic function thereof and transmits an output signal at an external output terminal OUT. When the timing at which a signal (x) rises to a high level is measured under an input condition a specified by a tester, a relative quick timing signal phi as shown by 1 is generated. Then, a flip flop circuit FF which should bring in the signal (x) is selected with a multiplexer MPX, which sends out the output signal at a measuring terminal T. The level of the measuring terminal is decided on with a tester. Receiving the results, the tester sets an input condition again and performs the same decision by the timing signal phi slightly delayed as shown by 2. Likewise, the timing signal phi is delayed sequentially until the signal transmitted from the measuring terminal T reaches a high level.

Rotary encoder device

Abstract: PURPOSE:To obtain discrimination information of a rotation direction in addition to information about the number of revolutions by adding a logic circuit having a simple constitution and an up/down counter to a rotary encoder. CONSTITUTION:Output pulse signals 1 and 2 different in phase are applied from a rotary encoder 10 to terminals A and B. Waveforms 3 and 4 are obtained as output waveforms of an R-S flip flop 30 consisting of NAND circuits 21 and 22, and the signal 3 which is outputted to a terminal C at a leading edge (a) of an output signal 5 of a NAND circuit 23 has logical level ''O'' in case of application of a clockwise rotation pulse and has logicl level ''1'' in case of application of a counterclockwise rotation pulse. The up/down mode of an up/down counter 11 is set by the output of the terminal C, and the output of a terminal D is used as a count input to count pulses.

Semiconductor integrated device

Abstract: PURPOSE:To obtain the titled device having a simple and small-sized circuit for diagnosis by a method wherein the first means putting the output of a flip flop in high impedance and the second means blocking input signals are made to function during failure diagnosis. CONSTITUTION:Gates 50 and 51 forming the flip flop, a 2-channel multiplexer 52, a control circuit for diagnosis 53, and control switches 54 and 55 are provided. In logical action mode, the multiplexer comes to operation state by a control signal 57; accordingly, the device performs normal logical actions on the basis of set signals S1 and reset signals R1. On the other hand, in diagnosis mode, the multiplexer shields the input signals R1 and S1 by the action of the signals 57, transferring diagnosis data signals into a closed loop constructed by the gates, and holding the signals in the flip flop. Thus, the states of output terminals Q1 and -Q1 of the flip flop are successively checked.

Cathode-ray tube oscilloscope

Abstract: PURPOSE:To display individual channel signals in time division mode in the transverse direction by providing a timing pulse generating circuit with a flip flop circuit, AND circuit, and OR circuit and displaying plural channel signals for one sweep on a cathode-ray tube. CONSTITUTION:A timing pulse generating circuit 14 is provided with four flip flop circuits (F.F circuits) 31-34 which transmit driving pulses to NOT circuits 21, 24, 27, and 30 successively to perform switching operations of four transistors TRs 19, 22, 25, and 28, an AND circuit 35, an oscillator 36 which gives clock pulses to these F.F circuits, an OR circuit 37 which converts four driving pulses from F.F circuits to continuous pulses for X-axis sweep and outputs them to an amplifying circuit of a device body, etc. Thus, the waveforms of plural channel signals are displayed for one X axis on the cathode-ray tube, and a reset section where no waveforms are displayed appears between optional adjacent channel signal waveforms.