Showing papers on "Flip-flop published in 1987"

Metastable resistant flip-flop

Abstract: A flip-flop circuit has two D type flip-flops. A common system clock drives both flip-flops. A stream of asynchronous data is connected to the data input of the first flip-flop FF1. The output of FF1 is connected to the data input of the second flip-flop FF2. The timing characteristics of FF1 and FF2 are chosen so that the time from the clock pulse to the high logic output of FF1 plus the set up time of FF2 is less than the minimum propagation delay time of FF2.

Phase-selectable flip-flop

Abstract: A phase-selectable flip-flop has an input dual-enable transparent latch and an output D-type flip-flop. A clock is input to one enable of the transparent latch and to the flip-flop, and a command is input to the second enable of the transparent latch. When the command is in a first state the latch is held transparent and data is clocked into the flip-flop on the rising edge of the clock, and when the command is in a second state data is held by the transparent latch on the falling edge of the clock and clocked into the flip-flop on the succeeding rising edge.

Flip-flop circuit with short propagation delay

Abstract: In a flip-flop circuit, input and output terminals of two inverters connected between corresponding data input terminals and corresponding data output terminals are cross-connected. Latch switches are inserted between the inverters and the corresponding data input terminals. Hold switches are inserted in the cross-connected portion of the two inverters. The latch switches are turned on/off in synchronism with a latch input while the hold switches are turned on/off in synchronism with a hold input.

Oscillation circuit of microcomputer

Abstract: PURPOSE:To reduce electromagnetic-wave disturbances to peripheral equipment from an oscillation circuit used in a microcomputer, by dispersing the spectrum distribution of the higher harmonic component of the electromagnetic waves. CONSTITUTION:Delay circuits 121-125 which are selected by means of switches SW1-SW5 are provided and the selection is made in accordance with outputs of shift registers 13. Then the output of the delay circuits is inputted to a control section 10 after they are combined to an output f1 whose frequency fluctuates in the vicinity of f0 by an OR gate G1. The delaying times TD1-TD5 of the delay circuits 121-125 are set at random and the set delaying times Td1-TD5 are successively selected by the parallel outputs of the shift registers 13 which clock (CK) the f0. However, the shift registers 13 are cleared when read/write signals R/W from the microcomputer controlling section 10 become the write mode and all the outputs SW1-SW4 of flip flops FF1-FF4 of each stage are made zero. As a result, the output of an OR gate G2 and inverter I respectively become '0' and '1' and the flip flop FF1 of the 1st stage is set to '1'.

Flip-flop circuit

Abstract: PURPOSE:To reduce delay caused by the load of an FF circuit by connecting a gate circuit which controls the output of a master latch circuit and a slave latch circuit which is used only during a test to different output terminals of the master latch circuit respectively. CONSTITUTION:One input terminal of a gate 1 is connected to the output terminal Q of the master latch circuit LAT1 and the data input terminal D of the slave latch circuit LAT2 is connected to the output terminal Q. Further, one input terminal of a gate 3 is connected to the output terminal Q of the circuit LAT2 and a control signal and its inverted signal are inputted to other-terminal sides of the gates 1 and 3 respectively to control the output state of data. Thus, the gate 1 and circuit LAT2 are connected dispersedly to the terminals Q and Q of the circuit LAT1, so the side of the terminal Q of the circuit LAT1 drives only the gate 1 in normal operation. Consequently, the load on the output terminal Q is reduced and the delay due to the load is reduced.

Clock pulse generating circuit

Abstract: PURPOSE:To extend the effective clock pulse width while securing the non- overlap time, by adjusting the delay time of a variable delay circuit based on a pair of output pulses outputted from an RS flip flop circuit. CONSTITUTION:Output terminals and the other input terminals of a pair of NOR gate circuits G1 and G2 are connected crosswise through variable delay circuits VDLY1 and VDLY2 to constitute the RS flip flop circuit. Two-phase clock pulses phi1 and phi2 are outputted from output terminals of NOR gate circuits G1 and G2. That is, variable delay circuits VDLY1 and VDLY2 whose delay time is controlled based on a pair of output pulses outputted from the RS flip flop circuit are provided on the feedback path of the RS flip flop which receives the single-phase clock signal and its inverted signal. Thus, a pair of output pulses based on output pulses are monitored to set a required minimum delay time free from overlap, and the effective pulse width is extended.

Automatic switching method for video signal

Abstract: PURPOSE:To automate a video switching circuit so that complicated and prompt switching operations required when the output of a VTR is used as an input picture can be made unnecessary, by controlling a flip flop circuit by using synchronizing signals separated from TV video signals CONSTITUTION:Video inputs A, B, and C are respectively supplied to synchronizing separator circuits 5 and synchronizing signals separated by the separator circuits 5 are supplied to integration circuits 6 Outputs of the integration circuits 6 are supplied to a flip flop circuit 7 and the flip flop circuit 7 is controlled by the presence and absence of the signal input Namely, when the synchronizing separator circuits 5 separate and integrate the synchronizing signals, the flip flop circuit 7 discriminates the presence/absence and order of the input signal and upon discrimination, a switch 8 is turned on and one of the video inputs A, B, and C is led to a monitor TV set 9 Thus switching operations are performed

Tuning characteristics and inverter/inverted-output flip-flop operation of tandem-electrode laser diode

Abstract: The letter discusses the novel bistability which is experimentally observed in the tuning characteristic of a tandemelectrode laser diode (TE-LD). Using this tuning characteristic, inverter and inverted-output flip-flop operations are demonstrated between the source LD driving current and the TE-LD optical output. The tuning characteristic is applicable to optical logic devices having the inverter function.

Fault detection circuit

Abstract: PURPOSE:To detect a fault such as the stop of a whole register circuit, i.e. a fault in a clock distribution circuit, by adding a flip flop (FF) of which status value is inverted at every clock to the register circuit and forming a comparator for comparing the values of respective FFs in plural register circuits. CONSTITUTION:If it is supposed that a clock signal line 20 is failed, the operation of a register circuit 1 is stopped because of no supply of clocks and an operation display signal 30 outputted from an operation display FF 10 becomes a fixed value. On the other hand, register circuits 2, 3 are independent of said fault and continue normal operation, so that their operation display signal are continuously inverted at every generation of a clock. Thereby, the comparator 4 can detect the discrepancy of input signals at every two clocks and inform the fault in any one of the registers 1-3 to an external circuit through an output terminal 43. When any one bit of an output from clock signal lines 21, 22 or a clock distributing circuit 13 is failed, similar operation is executed.

Electronic control circuit for command systems

Abstract: A control circuit for a closed loop command system having an output which is adjusted to conform with an input command level. A pulse generator provides digital pulses with durations representative of the output of the system. Command pulses are generated by the system pulses and have durations representative of the input command. Each pulse is applied to logic gating along with the complement of the other pulse, with the logic gating providing a signal indicating whether the system pulse or the command pulse is longer. The last gate signal is retained in a flip flop memory and is used to adjust the output power level up or down depending upon the result of the pulse length comparison.

Latching circuit, and flip-flop circuit using this latching circuit

Abstract: PURPOSE:To execute a high speed operation by connecting each input terminal and output terminal of two clock gates, respectively, and providing a data transfer gate on each connecting point of the input terminal and the output terminal, respectively. CONSTITUTION:When a clock signal phi becomes '1', a data DI and an opposite phase DI are supplied to nodes N3, N4 through clocked inverters 171, 172 (data transfer gates), respectively. When a clock signal of an opposite phase becomes '1', the potential of the nodes N3, N4 are amplified and latched by clocked inverters 181, 182 (clocked gates). In this case, even if a circuit threshold value of the inverters 171, 172 is varied, these nodes N3, N4 are corrected to a correct potential immediately by the inverters 181, 182, if a magnitude relation of the potential of the nodes N3, N4 is correct. In this way, a high speed operation can be executed.

Flip-flop circuit

Abstract: PURPOSE:To constitute the circuit of a small quantity of the circuit element and to make it into the circuit suitable to a high integration by constituting an edge trigger type flip-flop circuit of an inverter circuit and plural switches MOSFET to change the connecting condition of the inverter and shift the input data CONSTITUTION:For an edge trigger type flip-flop circuit, inverter circuits N1 and N2 to constitute the latch when a clock pulse CK is a high level and an inverter circuit N3 to constitute the latch with the inverter circuit N2 when the clock pulse CK is a low level are of the basic constitution A P channel MOSFET 11 and an N channel MOSFET Q1' are connected to the parallel mode, and functions as a switch MOSFET to input the inverting signal by an inverter circuit N0 of input data Din to the inverter circuit N1 To the gate of the P channel MOSFET Q1, the clock pulse is supplied, to the gate of the N channel MOSFET Q1', a clock pulse, the inverse of CK is supplied respectively, and when the clock pulse CK is a low level, both MOSFET are turned on

Flip-flop circuit

Abstract: PURPOSE:To prevent the generation of a malfunction without requiring a change of a gate length and a gate width of a transistor, by providing two pieces of composite logic circuits. CONSTITUTION:The first composite logic circuit 23 in which the first plural OR input terminals are connected to a reset signal input terminal IN3, and the second composite logic circuit 24 in which an output terminal is connected to the second data output terminal OUT2 are provided. When a reset signal 03 is a low level, it is reset, but the reset signal 03 is supplied to all input terminals of a multi-input OR circuit of the composite logic circuits 23, 24. By replacing an input terminal to which a reset signal of a two-input NAND circuit for receiving said reset signal has been inputted, with the multi-input OR circuit, and also supplying the reset signal to all input terminals of the multi-input OR circuit, a logical threshold voltage in the reset signal input terminal can be dropped without changing a gate length and a gate width of a transistor.

Master-slave flip flop

Abstract: PURPOSE:To obtain a master-slave flip flop capable of diagnosing the fault of an LSI and is equipped with scan in/out function, by adding gates constituted of transistors to the master-slave flip flop constituted of an ECL circuit. CONSTITUTION:A gate group 13-18 are composed of transistors, etc. A D-type latch circuit 11 can fetch data SD for scan by triggering them with clocks SCK for scan at the time of tests in addition to system data D. At the time of normal operation, the system data D are triggered by system clocks -CKA and this master-slave flip flop is operated. When clock controlling signals DG are set to a logically high level at the time of a fault diagnosis, supply of the clocks -CKA to the latch circuit 11 can be interrupted and the latch circuit 11 can be triggered by clocks CKB instead of the clock -CKA.

Flip-flop circuit

Abstract: PURPOSE:To increase the maximum operating frequency by connecting a resistor and a peaking circuit in series as a load of a differential pair transistor (TR) so as to cancel the effect of the stray capacitance in existence to the collector of the differential TR. CONSTITUTION:The impedance viewing toward the emitter of a TR Q9 at a prescribed high frequency region is inductive in a circuit comprising the load TR Q9 and resistors RC1, RB1 in an emitter coupling logic FF circuit subject to circuit integration to form a peaking circuit 10 having a characteristic known as the peaking characteristic. Similarly, a load TR Q10, resistors RC2, RB2 form a peaking circuit 11 similarly. Thus, the effect by the stray capacitance existing between collector connecting points N1, N2 and the ground is cancelled. Thus, the frequency characteristic of the FF circuit is improved and the self-running frequency being an indication of the maximum operating frequency is improved remarkably. Even with a clock input exceeding 1MHz, the circuit is operated stably.

Flip-flop circuit

Abstract: PURPOSE:To realize a flip-flop without requiring an analog trigger pulse generator and inhibition input by using logic circuits only so as to constitute a flip-flop circuit. CONSTITUTION:The flip-flop circuit consists of a master flip-flop 1, slave flip- flops 22, 23, invertes 24, 25 and AND gates 26, 27 for input transfer. When a set signal S0 changes from L to H, the output of a AND gate 26 changes from L via H into L. Further, the output of the AND gate 27 goes from L via H into L in response to a reset signal R0 changed from L to H. Thus, since a pulse input is fed to input terminals R, S of the master flip-flop 1, no inhibition input exists in signals R0, S0. Further, it is known that the width of the input pulse at terminals R, S is the minimum time completing the circuit operation.

Circuit arrangement for the digital measurement of the angular velocity and angular acceleration of rotating machines

Abstract: The invention relates to a circuit arrangement for the digital measurement of the angular velocity and the angular acceleration of rotating machines, in particular of electric motors, which is installed in or connected to the data-fixing external circuits, sensors and other circuits (memories, datbuses, counters etc.). The circuit arrangement is characterised in that the output of a sensor 1 mounted on the shaft of the machine to be tested is connected to the input of a signal conditioner 2 whose output is connected to the time input of a D flip flop 3 and to the input of cycle counters 4, in that the output of the cycle counters 4 is connected to a databus 5 belonging to a microcomputer system and the databus 5 is connected to the input of a RAM memory 6 belonging to the outer system, in that the output of the quartz-controlled time marker generator 9, which is built into the circuit arrangement 18, is connected, on the one hand, to the input of an elapsed-time counter 8 and, on the other hand, to the input of a measurement control circuit 9 and the outputs of the elapsed-time counters 8 are connected to the databus 5, in that one of the outputs of the measurement control circuit 9 is connected via an invertor 10 and the other is connected directly to respectively one input of NAND circuits 11 and the signal output T DELTA of the measurement control circuit 9 is connected to the other input of the NAND circuits 11, in that the outputs of the NAND circuits 11...to the D input of the D flip flops 3... Original abstract incomplete.

Flip-flop logic circuit

Abstract: PURPOSE:To eliminate the need for a delay circuit with large scale even when a high speed logic element is employed by selecting the width of a clock signal larger than the sum between a clock signal skew DELTAt and a holding time th of the post-stage FF CONSTITUTION:A delay circuit 31 is connected between the output of a FF 12 and an input of a FF 14 When a clock signal 18 descends, an input signal (data D1) 11 is inputted to the FF 12 at a point of time t1, an output signal 19 is obtained and a P-channel transistor (TR) 32 is turned off by the clock signal 18 inputted to the delay circuit 31 at the same time and an N-channel TR is turned off Thus, the output signal 22 of the delay circuit 31 holds a level (data D0) just before the clock signal 18 descends When a clock signal rises, a level (data D1) of the output signal 19 is outputted inversely at a point of time t2 as a delay output signal 22 and set to the FF 14 at the fall of the next clock signal 21 Thus, the output signal of the FF 12 is delayed by the clock pulse width, the holding time th is satisfied to guarantee the normal circuit operation Thus, the delay of the clock signal width is obtained always and the circuit is constituted by the prescribed number of elements independently of the holding time th

Optical t flip-flop circuit

Abstract: PURPOSE:To obtain a totally optical type optical TFF circuit which is sized small and suits to integration by using an optical switch and a positive and a negative type optical bistable element. CONSTITUTION:Optical input conditions are so set that positive type optical bistable elements 50 and 51 have an AND function, a negative type optical bistable element 70 has a NOT function, and positive type and negative type bistable elements 60 and 80 have a memory function. A directional coupler type optical switch is used as the optical switch 90 and a voltage signal CP is applied to control electrodes 95 and 96 to place the optical switch in two states. Namely, they are a bar state wherein a light signal from an input terminal 91 is guided to an output terminal 93 and a light signal from an input terminal 92 is guided to an output terminal 94 and a cross state wherein the light signal from the input terminal 91 is guided to the output terminal 94 and the light signal from the input terminal 92 is guided to the output terminal 93. The respective functions of those elements and optical switch are integrated on one substrate to attain size reduction, and there is no electric circuit interposed, so the totally optical type optical TFF circuit is realized.

Clock asynchronism detection circuit

Abstract: PURPOSE:To detect asynchronism of clocks correctly even if input clocks include jitter, by inputting the output of a logic circuit, which outputs a signal which is made wider by a certain range before and after a stable point of the clock synchronous state, to a phase comparator as the data input CONSTITUTION:An input clock 9 of a gate circuit 100 and write clocks 11-5 and 11-8 are inputted to a gate circuit 108, and the circuit 108 outputs a signal 17(b-1) Input signals (a-1), (a-2), and (b-2) of the first phase comparing circuit are a write clock 11-1 and a read clock 13-1, and signals (b-1) and (b-2) are inputted to the second phase comparing circuit 105 consisting of a flip flop to compare phases, and the signal (b-1) is read with the signal (b-2); and therefore, logical '0' is always outputted even if the phase difference between the first clock 9 and the second clock 12 is fluctuated relatively to +4--35 bits, and clocks asynchronism is detected correctly even for 2-fold conventional phase fluctuation

Dynamic type set/reset flip-flop

Abstract: PURPOSE: To realize a dynamic type FF to execute a set and a reset with a simple circuit constitution by cascade-connecting first and second clocked CMOS NOR gates. CONSTITUTION: A Set signal is used as a first control signal, and a Reset signal is used as a second control signal. Then, first, a first clocked CMOS NOR gate 20 fetches data and the Set signal in synchronizing to a first clock pulse, and outputs the NOR of both. Next, a second clocked CMOS NOR gate 30 fetches an output signal from the first clocked CMOS NOR gate and the Reset signal in synchronizing to a second clock pulse, and outputs the NOR of both. COPYRIGHT: (C)1989,JPO&Japio

Optical s-r flip-flop circuit

Abstract: PURPOSE:To obtain a totally optical type S-RFF circuit which is sized small and suits to integration by using an optical switch, and a positive and a negative type optical bistable element. CONSTITUTION:Optical input conditions are so set that a positive type optical bistable element 50 has an AND function, a negative type optical bistable element 70 has a NOT function, and positive and negative type bistable elements 60 and 80 have a memory function. Further, a directional coupler type optical switch is used as the optical switch 90 and a voltage signal CP is applied to control electrodes 95 and 96 to place the optical switch in two states. Namely, they are a bar state wherein a light signal from an input terminal 91 is guided to an output terminal 93 and a light signal from an input terminal 92 is guided to an output terminal 94 and a cross state wherein the light signal from the input terminal 91 is guided to the output terminal 94 and the light signal from the input terminal 92 is guided to the output terminal 93. Respective functions of those elements and optical switch are integrated on one substrate to attain size reduction, and there is no electric circuit interposed, so the totally optical type optical S-RFF circuit is realized.

Variable stage number shifting circuit

Abstract: PURPOSE:To simplify the circuit configuration of a variable stage number shifting circuit whose data word length of input signals is (n) and longest shift stage number is (m), by constituting the circuit of (n) pieces of blocks, in each of which a circuit composed of a flip flop circuit and gate is connected in (m) stages, and one piece of decoder circuit. CONSTITUTION:Clock signals are inputted to gates 5 and 6 of the initial stage and the gate outputs of the preceding stage are connected to gates 7-14 of the succeeding stages. Clock signals are supplied to flip-flop circuits 1-4 of each stage from corresponding gate outputs. A control signal which is given in k-bit binary code is converted into a thermometer code signal which produces a signal having a bit width of 2k digit and corresponding to the digit of the input control signal by means of a decoder circuit 15 and, by controlling the clock by supplying the output of the decoder circuit 15 to the gates of corresponding stages, clocks are supplied to flip-flop circuits corresponding to an optional shifting stage number only. Then the level of a clock input terminal is fixed so that the master flip-flop circuits and slave flip-flop circuits of the succeeding flip-flop circuits can be set to through-modes and output signals are obtained from the output terminal of the flip-flop circuit of the final stage.

Division for combination circuit of sequence circuit

Abstract: PURPOSE:To achieve a higher speed of diagnosis of a large logical circuit, by finding a sequence circuit searching a loop matrix of directed graph to divide it into blocks of a combination circuit. CONSTITUTION:A flip flop is made up of gates G14 and G15 and a trouble diag nosing of a logical circuit containing a loop connection for making a feed back from the gate G14 to a gate G8 is conducted with an electron beam tester, a laser probe or the like. With gates G1-G15 considered as contacts, the logical circuit is divided into blocks of a combination circuit detecting the existance of a loop of a partial graph generated with inter-gate nets 1-29 made corre sponding to directed branches in such a manner that each line of the loop ma trix will surely contains 1 and -1 1 elements. The partial graph is formed by adding directed arms and contacts along the direction of the circuit from input terminals a-o. Furthermore, when additional arms are provided to form a large graph, the arm finally added shall be arranged to be a cut branch be tween the blocks if the element of each line in the matrixes is neither 1 nor -1 with the addition thereof.

Flip-flop circuit

Abstract: PURPOSE:To decrease the number of elements by providing an FF circuit which has no resetting function basically with an N channel transistor (TR) where the state of a transfer gate is fixed at the time of resetting, and providing a means which adds a reset circuit to a master side FF circuit. CONSTITUTION:A CMOS type FF circuit consists of the master-side FF circuit 30 having a reset circuit and a slave-side FF circuit 31 having no reset circuit and the circuit 30 has an N channel TR 40. When a clock signal and a reset signal are supplied, a NOR circuit 22 turns off transfer gates 1 and 4 and turns on transfer gates 2 and 3. At this time, the circuit 30 is in a hold state and the TR 40 is on, so an output Q at a low level. When an initial value is at a high level, the P channel TR of an inverter 15 is on, so the driving capability of the TR 40 is increased sufficiently and a voltage lower than the switching voltage of an inverter 10 is inputted.

Method for constituting counter in semiconductor integrated circuit

Abstract: PURPOSE:To easily constitute an optional counter, by mutually connecting the specific 1st and 2nd logic circuit with flip flop circuits. CONSTITUTION:The 1st logic circuit block 1 is composed of inverter gates 11a-11e, NAND gates 12a-12d, exclusive OR gates 13a-13c, and an exclusive NOR gate 14. The 2nd logic circuit block 2 is composed of inverter gates 21a-21e, NAND gates 22a-22d, exclusive OR gates 23a-23c, and an exclusive NOR gate 24. When the 1st and 2nd logic circuits 1 and 2 and edge-trigger flip flop circuits 3a-3c are mutually connected by combination, an up counter, down counter, and up-down counter can be constituted easily.

Flip-flop circuit

Abstract: PURPOSE:To obtain the circuit with high reliability without causing malfunction by inserting a logic circuit activating/inactivating to a cross coupling path on the way of the path of a master flip-flop based on an output signal of a slave flip-flop and a clock signal CONSTITUTION:An AND gate 1 and a NOR gate 3 constitute the 1st composite inverse logic circuit 21 and an AND gate 2 and a NOR gate 4 constitute the 2nd composite inverse logic circuit 22 Their input/output terminals are coupled in crossing to constitute a master flip-flop 31 and AND gates 5, 6 and OR gates 51, 52 are inserted on the way of the coupling path An OR gate 7 and a NAND gate 9 constitute the 3rd composite inverse logic circuit 23 and an OR gate 8 and a NAND gate 10 constitute the 4th composite inverse logic circuit 24 Their input/output terminals are coupled in crossing to constitute a slave flip-flop 32 Thus, before positive feedback from the slave flip-flop 32 is established, the positive feedback is established forcibly by using a clock signal CK, then no malfunction is caused

Time code field detecting circuit

Abstract: PURPOSE:To rapidly carry out a highly accurate editing operation by providing a comparator circuit for transmitting an output when the output of a divider making the contents of a memory of a latch circuit 1/2 coincides with the output of a counter circuit. CONSTITUTION:The latch circuit 2 latches an N-bit count output signal (b) of the counter circuit 1. The divider 3 makes an N-bit latch output signal C of the N-bit latch circuit 2 1/2 and a magnitude comparator circuit 4 compares a divider output signal (d) of the divider 3 with the N-bit count output signal (b) of the counter circuit 1. A flip flop circuit 5 reset by a frame signal (g) extracted from a time code signal supplied from an input terminal 201 and set by a coincidence signal (e) of the N-bit magnitude comparator circuit 4 outputs a field display signal (f) to an output terminal 301 and the N-bit counter circuit 1 and the N-bit latch circuit 2 are respectively latched by the frame signal (g).

Multi-input josephson decoder circuit

Abstract: PURPOSE:To constitute a multi-input OR type decoder, by adding one or more current flip flip circuits to the previous stage of an OR type decoder circuit consisting of one stage of current (transfer type) flip flop circuit. CONSTITUTION:A 6-to-64 decoder, with which 64 kinds (2 =64 combinations) of outputs are selected by using six address inputs A0, A1, A2, A3, A4, and A5 is shown here. Firstly, address signals the inverse of A0, the inverse of A1, and the inverse of A2 and the inverse of A3, the inverse of A4, and the inverse of A5 are respectively given to the two preceding-stage current flip flops and each output is given to the OR gate of the final-stage current flip flop. When the output of this decoder is fetched from the branch on the OR gate side of the final-stage current flip flop 1, the A0, A1, A2, A3, A4, and A5 are obtained. When the number of the preceding-stage current flip flop is increased in such way, the number of addresses can be increased.

Binary flip-flop comprising cmos semiconductor device

Abstract: PURPOSE:To prevent surely the racing by providing a smoothing circuit smoothing the output of a binary flip-flop and an integration integrating a smoothed output CONSTITUTION:Two clocked inverters 11, 12 consist respectively of four transistors (TRs) whose switch periods are connected in series When a clock signal CK is at a low level, an inverted clock signal, the inverse of CK is at a high level and the 1st clocked inverter 11 is operated but the 2nd clocked inverter 12 is inoperative On the other hand, an inverter 13 is always in operation If the timing of the inverted clock signal, the inverse of CK is deviated, an output A of the inverter 13 restores to a low level when the high level is sufficiently to be maintained The output A is smoothed as a mean level by a smoothing circuit 21 and a desired reverse bias voltage B is formed The reverse bias voltage B is stored in a succeeding integration device 3 and fed to the TRs successively