Showing papers on "Flip-flop published in 1989"

Edge triggered d-type flip-flop scan latch cell with recirculation capability

Abstract: A synchronous latch device macrocell which includes an input gate section and a scannable latch section. Both sections are directly connected together to provide a non-inverting path for input data signals thereby eliminating the need for internal inverting buffer circuits. The non-inverting output of the latch section connects to an output pin and provides a signal representation of the state of the latch device. The output pin is externally connected through a conductor wire to either one of a pair of complementary data input pins of the input gate section. The connection made is selected as a function of which data input pin connection provides the faster loading of the latch device as viewed from the source of the signal applied to the load control pin of the input gate section.

Non-volatile ram with integrated compact static ram load configuration

Abstract: A non-volatile random access memory (NVRAM) cell of condensed size employs a pair of programmable threshold voltage devices, e.g. MNOS (metal nitride oxide semiconductor), SNOS (silicon nitride oxide semiconductor), SONOS (silicon oxide-nitride-oxide semiconductor) or floating gate transistors, in which different threshold voltage levels are established in accordance with the data signal levels existing on the data nodes of a flip flop, when the volatile data is stored in the programmable devices. During recall of the non-volatile stored data to the data nodes of the flip flop, the programmable devices actively conduct current to the data nodes to set the flip flop in the same state that existed when the data was stored. Power is supplied to the flip flop independently of the power supplied to the programmable devices. A single polysilicon conductor forms gates of transistors which connect the programmable devices to the data nodes and the gates of the flip flop transistors. A load device for each data node is integrated in the single polysilicon conductor. A dynamic program inhibit capability is achieved in each programmable device during the store operation, by applying a series of programming signal pulses.

Flexible imbedded test system for VLSI circuits

Abstract: A logic chip contains a plurality of ranks of flip-flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in parallel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units. It is adaptable to custom or semi-custom VLSI chip design and it teaches that any "component" (for example, a logic unit or a single element) may be tested individually using two data paths (one for test and one for operation or normal data). The test data output can be transmitted in parallel between the flip flop ranks, or it can go serially through the flip flop components of a given rank.

Multifunction flip-flop-type circuit

Abstract: A flip-flop-type circuit capable of operating either as a conventional D flip-flop or as a device which merely passes through the data applied to it (so-called "flow-through mode"). In the flow-through mode, the circuit has the additional capability of being able to latch in the data flowing through it at any time. Thus the circuit can also operate as a level-sensitive latch.

Dual triggered edge-sensitive asynchrounous flip-flop

Abstract: An architecture for bistable circuits with minimized sensitivity to metastability events and with improved operation in signal timing, arbitration, and protocol applications. Conventional edge-triggered flip-flops require input signals to remain present during certain set-up and/or hold time intervals on an input line "data path" for sampling at an instant determined by a separate synchronization input signal. In contrast, the present invention uses two edge-sensitive input lines which are triggered essentially independently without either being synchronized by or depending upon the other. The flip-flops also have twin, independently operable, level sensitive and selected priority PRESET and CLEAR input lines. The active edge or level polarity is programmable for each input line. Alternate embodiments for complementary classes of asynchronous timing perform specific bistable functions, such as set-reset, or toggle.

Toggle-free scan flip-flop

Abstract: A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic. Thus, the logic under test is not affected by the loading of the scan test vector, since the parallel system output Q of the TFSFF does not toggle during the shifting sequence.

Metastable-proof flip-flop

Abstract: A bistable, clocked or synchronous electronic flip-flop device (10) having a unique circuit architecture which precludes the possibility of the flip-flop having any metastable output states, independent of the polarity, amplitude or duration of data input signals, or their time relationship to the external clock signal applied to the flip-flop. This metastable-free operation is accomplished by a circuit architecture which performs the data signal processing steps of (a) logically gating input data (D) to produce a predetermined voltage level only if the input data logic level is different than the existing logic level of the flip-flop device output, (b) storing the resultant voltage level in a sample-and-hold device (23) which is disconnected from the input source immediately after the active edge of the external clock (C), then (c) generating an internal data clock (33) only if the stored voltage level is sufficiently near a predetermined threshold level to indicate that the input logic level is different from the present logic level of the device, and (d) using the internal data clock (33) to toggle a pair of bistable elements (20, 37) in a toggle configuration which then always reflects the correct state as driven by the input data but having no exposure whatsoever to data input irregularities of amplitude and/or timing which contribute to metastability in conventional flip-flop devices of the prior art. Methods for storing digital data in a clocked electronic bistable device that provides immunity from metastability are also disclosed.

Output circuit for a programmable logic array

Abstract: An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, and clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

High-speed low-power flip-flop

Abstract: A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal The slave portion of the flip-flop includes a second bistable cell that is coupled to the first cell and a second control circuit for changing the state of the second cell in response to the output of the first cell and to a clock signal The flip-flop is intended to be implemented using CMOS technology, and is capable of performing at frequencies greater than a gigahertz with low power consumption The circuit configuration is highly symmetric, so that the master and slave portions may be interchanged

Asynchronously loadable D-type flip-flop

Abstract: A conventional D-type flip-flop transfers the data input D to a first output Q and a second output Q', where the second output Q' is the complement of the first output Q, on the transitions of a clock signal CK. This involves the transfer of data from a master latch and a series-connected slave latch which are loaded on alternating phases of the clock signal CK. The present invention provides for asynchronous loading of replacement data into the flip-flop by using a tri-stable buffer in both the master and slave latches. In response to a load signal LD, replacement data is injected into the master and slave latches overriding the current value stored at the Q and Q' outputs. This occurs because the load signal disables the normally active buffers while activating the loading buffers causing the normally active data path to go the tri-state condition. The state of the clock signal CK is of no importance to the outcome of the asynchronous load operation since both the master and the slave latch are overwritten during the load phase.

Semiconductor integrated circuit

Abstract: PURPOSE:To compensate for any uncertainty in simulation and thus to perform an optimal control of signal transfer characteristics of inter-element wirings within circuits for signals supplied from an external terminal on a device by inserting a switching element and a capacitor connected in series between an arbitrary wiring and a ground within a chip, and providing a plurality of circuits which control the opening and closing of the switching element from the external input terminal. CONSTITUTION:A plurality of circuits are provided in which a source of an N-channel MOS transistor 3 is connected to a wiring to be controlled which is connected to a clock input of a D flip flop, its drain being connected to a ground 5 via a capacitor 4, its gate being connected to an external input terminal 1. The circuit between the source and drain of the N-channel MOS transistor 8 is opened and closed by the control from the internal input terminal 1, the number of switches to be opened and closed can arbitrarily be specified by the external input terminal. As a result, a time constant of the circuit between the MOS transistor 3 and the capacitor 4 connected in series between the clock wiring and the ground varies, whereby the signal transfer delay characteristic varies and emulation between the data and the clock can be avoided.

Metastability of CMOS latch/flip-flop

Abstract: The authors present several design issues for CMOS latch/flip-flops designed for metastable-hardness, regarding optimal device size, aspect ratio, and configurations. They use AC small-signal analysis in the frequency domain rather than the time domain. This design approach is verified experimentally. The power-supply disturbance and temperature variation effects on the metastability are measured and the measurement data confirm that a reduced power supply voltage and a higher temperature cause a lower metastable resolving capability

Time difference measuring circuit

Abstract: PURPOSE:To measure time difference between two signals by resolution higher than an input count pulse to a counter circuit by providing a first delay circuit to delay a measurement start signal and a second delay circuit to delay a count pulse. CONSTITUTION:The measurement start signal (a) is inputted to the delay circuit 9 that n-pieces of delay elements are connected in series, and delayed signals c1-cn are sent to a flip flop circuit 10, and a decoding circuit 11 converts the logical patterns of n-kinds due to signals d1-dn within time until the edge of the count pulse (b) arrives from the edge of the measurement start signal (a), and inputs them to an arithmetic operation circuit 15. Besides, the count pulse (b) is inputted to the same delay circuit 12 as the delay circuit 9, and the decoding circuit 14 converts the logical patterns of n-kinds due to the signals g1-gn within time until the edge of a measurement finish signal (e) arrives from a final count pulse edge which the counter circuit 7 counted. Thus, the time difference between two signals inputted to terminals 1, 2 can be measured by the high resolution.

Flip-flop circuit

Abstract: PURPOSE:To simplify a test by switching an FF circuit to a combinational circuit by switching input via a selector circuit. CONSTITUTION:Two-input NAND gates 12 and 13 and the selector circuits 14 and 15 are added on a D type FF circuit 11. Set input and data input are connected to the circuit 14 via the gate 12, and clock input and reset input to the circuit 15 via the gate 13, and the output Q, Q of the FF11 and that of the gates 12 and 13 are selected by switching mode switching input M1, and are outputted from the circuits 14 and 15. Thereby, since all of the sequential circuit groups 17 and 19 can be converted to the combinational circuit groups 16, 18, and 20 logically by the mode switching input M1 even in a circuit of logical construction in which the combinational circuit groups 16, 18, and 20 and the sequential circuit groups 17 and 19 are connected alternately, it is possible to generate a test pattern easily.

Re-triggerable monostable multivibrator capable of generating a predetermined width of pulse with additional logic gate and D flip-flop with reset

Abstract: A monostable multivibrator comprises an input circuit receiving an trigger signal for generating an instantaneous pulse, a timing generation circuit receiving the instantaneous pulse for generating a timing defining signal after a predetermined time, and an output circuit for generating a output pulse starting in response to the instantaneous pulse and terminating at the timing defining signal. The timing generation circuit includes a time constant circuit including at least a capacitor, an OR gate having a first input connected to receive the output signal of the output circuit, a first logic circuit operating to discharge the capacitor when an output of the OR gate is in a first level and to charge the capacitor when the output of the OR gate is in a second level opposite to the first level, a second logic circuit for generating the timing defining signal when the potential of the capacitor reaches a first predetermined reference voltage, a third logic circuit for generating a reset signal when the potential of the capacitor is higher than a second predetermined reference voltage which is higher than the first predetermined reference voltage, and a flipflop reset in response to the reset signal and driven in response to the instantaneous pulse. An output of the flipflop is connected to a second input of the OR gate. When the reset signal is not active, if the instantaneous pulse is applied to the flipflop, the output of the flipflop is brought to the first level, so as to cause the first logic circuit to forcibly discharge the capacitor of the time constant circuit. Thereafter when the reset signal becomes active, the output of the flipflop is brought to the second level, so as to cause the first logic circuit to forcibly charge the capacitor of the time constant.

Flip-flop circuit

Abstract: PURPOSE:To make the titled circuit suitable for high density circuit integration by forming a flip-flop circuit operated in two way so as to set freely the input/ output of a signal depending on the design status at that time CONSTITUTION:Two flip-flops 9a, 9b without directivity are constituted by inserting transmission gates 6, 7 in series with the output side of inverters 3a, 3d at the master and slave side not having the transmission gate in a conventional master slave flip-flop where inverters are connected as a loop and the flip-flops are connected in series Thus, the unit circuit being the input side is the master and the unit circuit being the output side is the slave circuit, the titled circuit is used in two-way and the input/output is set in matching with the other circuit, then the share of the circuit wiring occupied in the circuit is reduced and the degree of freedom in the design is improved

Redundancy decoder for an integrated semiconductor memory

Abstract: A redundancy decoder is used to address memory cells used in a redundant mode in an integrated memory. Each decoder stage (1) has a switching transistor (T) and a connector (F) that can be broken together with a control circuit (2) that is located between the two. The control circuit can be used during the test phase to check the stage is programmed, i.e. to check if the connector (F) is intact. The control circuit has a flip flop controlling a transistor and can be set and reset to allow simulation of the action of the connector.

Digital-to-analog converter

Abstract: A precision ratioed digital-to-analog data converter. A first latch stores a first digital word having a first numerical value and a second latch stores a second digital word having a second numerical value. A down counter alternately receives data from the first and second latches and is connected to a flip flop device to produce a waveform signal having first and second pulse components of opposite polarity. The first and second pulse components have a duration proportional to the first and second digital words. The output waveform is then inverted through an inverter comprising matched P and N channel MOSFETS. The inverted waveform is then presented to an RC integrator circuit which produces a DC signal. The DC signal is passed through a buffer amplifier connected in a voltage follower configuration.

D flip flop circuit with set/reset function

Abstract: PURPOSE:To increase the operation speed by combining clock inverters and pull-up and pull-down transistors TRs to provide a feedback inverter. CONSTITUTION:Clock inverters C11 and C12 are turned off at the time of set/ reset, and pull-up TRs P1 and P2 and pull-down TRs N1 and N2 are provided and a master part and a slave part are forcibly set or reset to transmit the input to the output. By the use of an edge triggered FF, a high-speed clock is used to transfer the input to the output. The master-slave system is adopted to eliminate the noise superposed on the input signal. Thus, the operation is quickly performed though set/reset functions are added, and the operation is quickly performed even in the set/reset state because it is sufficient if the input signal is delayed by one stage of TRs and one stage of inverters.

Test mode setting circuit

Abstract: PURPOSE:To simplify the circuit required for test of a logic system by inverting only the Q output of a desired D flip flop FF and setting a block corresponding to this D FF to the test mode. CONSTITUTION:In case of the test of a block 113 in the third stage, pulses of a scan clock terminal 6 and a scan-in terminal 7 are so controlled that only three pulses of the scan clock are sent after the scan-in pulse is inputted to the scan-in terminal 7. Q outputs of D FFs 91-9n successively got to the high level for every one scan pulse, and the scan operation is stopped when the Q output of the D FF 9n in the third stage goes to the high level. As the result, a test control circuit 103 is set to the test mode. Another block is selected by the same operation hereafter to execute the test.

Discriminating circuit for synchronizing signal polarity

Abstract: PURPOSE:To stably discriminate the polarity of a synchronizing signal by changing a synchronizing pulse duration by a time constant circuit consisting of a resistance and a capacitor and inputting the output and the synchronizing signal to a D flip flop. CONSTITUTION:The vertical or the horizontal synchronizing signal is inputted to a monostable multivibrator 4 from an input terminal 1. The trailing edge of the synchronizing signal is read by the monostable multivibrator 4 to output the pulse of the duration decided in the time constant circuit consisting of the resistance 2 and the capacitor 3 by defining the trailing edge to be a start from the monostable multivibrator 4. The output of the monostable multivibrator 4 is inputted to the clock input terminal CK of the D flip flop 5 and the synchronizing signal is inputted to the input terminal D. The DC signal of H or L level corresponding to the polarity the synchronizing signal is outputted from the D flip flop 5.

Variable power recorder for picture

Abstract: PURPOSE:To attain a micro variable power without damaging the definiteness of an output picture with a simple constitution by lowering a multiplication ratio in a multiplying circuit and making practical the frequency of a signal handled. CONSTITUTION:A rotary encoder 2 to synchronize and rotate to a drum outputs a clock signal Fin and the clock signal Fin is multiplied to 40 times by a PLL circuit 18 and becomes a practical clock signal Fout1 of 31.2MHz. The clock signal Fout1 is frequency-divided to 1/2 with the frequency-divider 7 in a variable frequency-divider 3, further, frequency-divided to 1/2 by a flip flop circuit 8 and becomes an output signal Fout2 corresponding to one dot of a reference. The frequency-dividing value of the frequency-divider 7 is set to a ROM 9 by a frequency-dividing value changing control means 4 and can be changed at any time. Thus, the highly accurate and micro variable power can be executed with circuit parts constitution commonly used.

Delay time checking system

Abstract: PURPOSE:To check whether or not the delay time of a signal from one flip flop circuit to the other flip flop circuit in a prescribed time by inputted clock signals having time difference mutually to the clock terminals of first and second flip flop circuits. CONSTITUTION:When the signal is transmitted from a first LSI 100 to a second LSI 200, first and second flip flop circuits 210 and 220 and an exclusive OR circuit 230 are provided in the second LSI 200. Further, the clock signals having the time difference mutually are inputted to respective clock input terminals 212 and 222 of the flip flop circuits 210 and 220. Thus, whether or not the delay time from a flip flop circuit 110 in the first LSI 100 to the first flip flop circuit 210 is in the prescribed time can be checked.

Phase and frequency detector

Abstract: A phase- and frequency-sensitive detector for digital clock pulses is known, which compares input clock pulses with reference clock pulses and, because of the ratio of the delay time, which occurs in the individual components of the detector, or of the pulse duration to the duration of the period does not allow the maximum clock pulse repetition rate still permissible in the individual components to be utilised. The detector according to the invention is improved with respect to the maximum clock pulse repetition rate which can be processed. Like the known detector, the new detector has two frequency divider circuits (1, 2) with cyclic counters (5, 6) and a bistable flip flop (9) at the output, the output signal of which is a measure of the existing frequency and phase deviation between input and reference clock pulses. According to the invention, it contains two logic circuits (7, 8) which obtain signals from the associated cyclic counters (5, 6) and from the outputs (Q, Q) of the bistable flip flop (9). The logic circuit (7, 8) prevents the continuation of the counting of the counter (5, 6), until a digital state at the output (Q, Q) of the bistable flip flop (9) is followed by a state which is complementary to this state.

Flip-flop circuit

Abstract: PURPOSE:To prevent the effect to be given on the characteristic of normal operation and to constitute a flip-flop circuit as a shift register by providing a terminal provided with a delay circuit and a terminal not provided to a shift-in input or an output of the flip-flop circuit possible for scan path constitution. CONSTITUTION:Flip-flop circuits 7, 8 have terminal SQ1, SQ2 supplying an output signal via buffers 10, 11 respectively. Selectors 5, 6 switch a normal signal and a signal at shift register operation. A terminal 1 is used for a scan-in signal, a terminal 4 is for a scan-out signal and a terminal 3 is used for a clock signal. A buffer 9 is a buffer to match the delay of the clock signal in the normal mode. In such a connection as above, even when the speed of the clock signal 8 is sufficiently faster than that of the clock signal 7, since the buffer 10 is provided, a flip-flop circuit 7 applies normal shift register operation to read a value before the flip-flop 8 is in operation.

A flip-flop arrangement.

Abstract: A delay type flip-flop arrangement using transistor-transistor logic receives a clock signal (CP) and input data (D) and outputs a logical output (Q) in accordance with the logic level of the data. The arrangement includes a master flip-flop (1) for transmitting a change in the logic level of the data to a pair of output ends (N1, N1) when the clock signal is at a predetermined logic level; a slave flip-flop (2) for latching the data transmitted via the pair of output ends; an output buffer (3) for effecting a buffering of the data latched in the slave flip-flop; and a drive circuit (4) for driving the output buffer. The drive circuit responds to logic levels of data (Q1, Q1) appearing at the pair of output ends of the master flip-flop and, based on the logic levels, drives the output buffer to determine the logic output (Q) to be output from the arrangement. This reduces the total propagation delay time and realises a high speed operation without increasing the power dissipation.

Scale generation circuit

Abstract: PURPOSE: To optionally select all musical intervals in a wider musical interval range by determining oscillation frequency and a frequency division ratio by a ROM. CONSTITUTION: The musical interval generating circuit is constituted of a NAND circuit 2, a plurality of inverters 3, 4, a resistor 1, a plurality of capacitors 5 to 16, a CR oscillation circuit consisting of a plurality of switches 17 to 28, a frequency dividing flip flop circuit 33, a plurality of programmable counters 30 to 32, a 1st decoder 36 for controlling the switches 17 to 28, a 2nd decoder 34 for controlling the counters 30 to 32, and a ROM 35 for determining the inputs of the decoders 34, 36. One of the capacitors 5 to 16 is selected by a signal read out from the ROM 35 to determine the oscillation frequency of the CR oscillation circuit, the frequency division ratio of the counters 30 to 32 is determined similarly by a signal read out from the ROM 35 and an optional sound interval can be generated from the combination of the oscillation frequency and the frequency division ratio.

Flip-flop test system

Abstract: PURPOSE:To execute a delay test by a ring oscilloscope in a logic circuit containing an FF by connecting an output terminal of a 2-multiplying circuit to a clock input terminal and connecting an input terminal of the 2-multiplying circuit to a data input terminal CONSTITUTION:A data input D of an FF 1 is connected to an input of a 2-multiplying circuit 8, and a clock input terminal CP of the FF 1 is connected to an output of the circuit 8 In this state, the circuit 8 operates so that an output frequency becomes two times of an input frequency When an output terminal of this circuit 8 is connected to a clock input of the FF 1, and the input terminal CP of the circuit 8 becomes a data input, the frequency of the clock input terminal of the FF 1 operates by two times of the input frequency An output waveform of the FF 1 which has been operated by this clock waveform becomes 1/2 of a clock waveform frequency, and becomes the same frequency as that of an input waveform As a result, the frequencies of the input waveform and the output waveform of the FF 1 coincide, and by returning this output to the input terminal CP, a ring oscillator can be constituted easily

Bi-cmos logic circuit

Abstract: PURPOSE:To considerably reduce the through current by allowing both outputs of a flip flop, whose both complementary outputs do not simultaneously go to the low potential level, to pass a CMOS logic part to drive a Bi-CMOS CONSTITUTION:First and second bipolar transistors TRs Q1 and Q2 longitudinally connected between power sources are driven by a CMOS logic output cd to obtain a logic output OUT in a connection part In this Bi-CMOS logic circuit, a flip flop(FF) 1 controlled by the logic input is provided in the input side Since a pair of logic gates 1a and 1b constituting the FF 1 controlled by an logic input IN form a crossing circuit where outputs of these gates are fed back to input sides of each other, both outputs (a) and (b) do not simultaneously go to the low potential level; and when both outputs are allowed to pass inverter gates 2a and 2b to drive TRs Q1 and Q2, TRs Q1 and Q2 are not simultaneously turned on, and the through current does not flow

Device of alarming during off of engine key

Abstract: PURPOSE:To prevent the occurrence of a risk, by a method wherein an alarm is generated during turning OFF of an engine key when completion of one of a fork, a shift lever, and a parking brake is not set. CONSTITUTION:When a fork is in a lower position, a shift lever is in a neutral position, and a parking brake is in a parking position, limit switches 5 and 8 and a photo switch 7, serving as respective position sensors, are all turned ON, and a logic signal 0 from a NAND circuit 31 is inputted to a D-type flip flop 32. Thus, even when an engine key 1 is brought into an OFF-state, the D-type flip flop 32 is not actuated. When either of the limit switches 5, 8 and the photo switch 7 is in an OFF-state, a logic signal from the NAND circuit 31 attains 1 and is inputted to the flip flop 32, and when the key switch 1 is turned OFF, the flip flop 32 is actuated, o controller 33 is started to generate an alarm.