Showing papers on "Flip-flop published in 1990"

Metastability of CMOS latch/flip-flop

Abstract: Optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops are obtained by using the AC small-signal analysis in the frequency domain instead of the usual time-domain approach. The Miller effect on the metastability is investigated for the configurations which have a better metastable resolving capability. The mean time between failure (MTBF) was measured, and the result verifies this new design approach. The power supply disturbance and temperature variation effects on the metastability were also measured, and the data show that a 0.75-V change of power supply voltage and 75 degrees C change of chip temperature cause a four orders of magnitude difference in the MTBF. The simulation results using the AC small-signal frequency-domain analysis agree well with the measurement data for the different power supply voltages and chip temperatures, confirming that an AC small-signal approach can be used more widely for the design of metastable hardened latch/flip-flops. The other parameters are discussed in terms of their effects on the latch/flip-flop's susceptibility to the metastable state. >

CMOS digital clock and data recovery circuit

Abstract: An integrated circuit for recovering the clock and data information from phase-encoded serial data The circuit includes a synchronous delay line coupled to a waveform digitizer and a waveform synthesizer The waveform digitizer receives and converts the phase-encoded data into a string of bits whose value represent the logic levels of an encoded data at T p /N intervals where T p is the reference clock period and N is the resolution of the waveform digitizer The encoded data may be one of several phase-encoded serial data such as Manchester coding The digitized output from the waveform digitizer is input to a transition detector, where the locations of the transitions (bit-boundary transitions and bit-center transitions) of the digitized encoded data are extracted An AND stage comprising N AND gates is coupled to the waveform digitizer and the waveform synthesizer for masking out the bit-boundary transitions and passes the bit-center transitions The output from the AND stage (a binary word) is coupled to a pair of encoders The encoders are coupled to an adder and an L-type register which are used for compensating for missing bit-center transitions or for the presence of two bit-center transitions A digital filter coupled to the L-type register allows the present invention to achieve lockon immediately and to filter out phase jitter The digital filter is further coupled to a shifter in the waveform synthesizer for synthesizing the clock information of the encoded data on one hand, and for providing mask bits to the AND stage on the other hand The clock information of the encoded data is synthesized by the shifter in the waveform synthesizer over a digital-to-time domain converter in the waveform synthesizer Finally, the data information of the phase-encoded serial data is regenerated by a D-type flip flop which receives encoded data over a delayed stage from its D input and also receives the clock information over its clock input

Single event upset hardening CMOS memory circuit

Abstract: A CMOS storage cell includes an n-channel storage circuit which has cross coupled n-channel storage transistors and a p-channel storage circuit including cross coupled p-channel storage transistors. Each of the n-channel storage transistors has an n-channel load transistor and each of the p-channel storage transistors has a p-channel load transistor. The n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit. The n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors. The storage cell can be used for a Static RAM or for a flip flop.

Master-slave clocked cmos flip-flop with hysteresis

Abstract: In a master-slave type flip-flop circuit comprising a master output holding circuit of the master stage circuit, the threshold value of the input circuit of the slave stage circuit has a hysteresis characteristic in which the high level threshold value is set to a higher value than the threshold value of the master output holding circuit and the low level threshold value is set to a lower value than the threshold value of the master output holding circuit. Due to the feature, a phenomenon is prevented in which the output is once inverted and then again inverted in the metastable state.

Metastable-immune flip-flop arrangement

Abstract: A D-Type flip-flop arrangement includes first and second latches (30, 46). Circuitry (44) interposed between the latches blocks any metastable condition that may occur in the first latch from propagating into the second latch. Additionally, the arrangement minimizes the likelihood that the first latch will enter a metastable condition and, if it does, resolves the condition extremely rapidly.

Code converting system

Abstract: PURPOSE:To digitally transfer a signal in a simple circuit constitution without using a special code converting circuit even when an interface code format is different by making the signals correspond to respective +1, 0 and -1 polarities of bipolar codes, and allocating the combination signals of '1' and '0' signals at two bits having the double converting speed of a bipolar code speed. CONSTITUTION:D flip flops 1 and 2 to make bipolar codes B and B into input signals, and fc into clock signals, an AND circuit 4, an OR circuit 5, and a D flip flop 6 to make the output of the OR circuit 5 into an input signal, and 2fc into the clock signal are used. Further, the combination codes of the '1' and '0' signals at two bits having the double transfer speed of the bipolar code speed are allocated. Thus, even when the interface code format is AMI, BnZS, HDBn, etc., the digital transfer is attained in the simple circuit constitution without using the special code converting circuit.

Novel ternary JKL flip-flop

Abstract: The logical design of ternary JKL edge-triggered flip-flop with triple-rail outputs is presented The computer simulation and experiment circuit made with CMOS gates show that the flip-flop can realise the expected logic functions

Low power master-slave S/R flip-flop circuit

Abstract: A clocked S/R flip-flop having a master stage driving a slave stage. A logic signal at either a set or reset input of the maser stage charges one of a pair of capacitors respectively coupled to the outputs of a pair of FET devices respectively connected to such inputs and which are enabled during a clock pulse. The clock pulse also disables a pair of bipolar transistors respectively coupled to the outputs of the FET devices. The falling edge of the clock pulse enables the bipolar transistors, and the one which is connected to the charged capacitor produces a logic signal at the input of one of a pair of cross-coupled CMOS logic gates which constitute the slave stage. This produces a logic signal at the output of the slave stage corresponding to the binary value of the logic signal applied to the set or reset input of the master stage. The combination of bipolar and FET devices for coupling the master stage to the slave stage achieves high speed operation with minimum power consumption, and only a single series of clock pulses is required to establish clocked operation.

Integrated logic circuit having plural input cells and flip-flop and output cells arranged in a cell block

Abstract: Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

Logic circuit which can be selected to function as a d or t type flip-flop

Abstract: A logic circuit comprises a first terminal for receiving an input data signal, a second terminal for receiving a clock signal, a first latch circuit coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal for outputting an output data signal which is output from the second latch circuit, and a selecting part coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode. The input data signal received by the first terminal selectively identifies one of the two modes of the flip-flop.

Clock distributing system

Abstract: PURPOSE: To obtain a clock signal whose skew in a chip is very small by changing the delay time in accordance with the output of a phase comparing circuit by a clock distributing circuit, which distributes a clock signal to one area, in the vicinity of the boundary of areas. CONSTITUTION: Small areas 140 and 141 where phases of clock signals should be compared are adjacent. Consequently, a phase comparing circuit 131 which compares phases of two clock signals with each other to output the result can be arranged in the vicinity of the boundary between small areas 140 and 141. As the result, proper flip flop groups 320 and 321 in small areas 140 and 141 are selected to input them to the phase comparing circuit 131 without extending connection lines 310 and 311. A delay control circuit changes the delay time of a distributing circuit 121 with variable delay circuit by a control signal 303. COPYRIGHT: (C)1992,JPO&Japio

Flip-flop circuit

Abstract: PURPOSE: To operate a latch circuit at a high frequency range by applying an external clock signal to a clock terminal of the latch circuit through a pulse generating circuit to allow the latch circuit to latch an input signal synchronously with a clock signal from the pulse generating circuit and to function a flip-flop circuit. CONSTITUTION: The flip-flop circuit is provided with a latch circuit 200 and a pulse generating circuit 201. An external clock signal is inputted from a terminal 16 to the pulse generating circuit 201, and a clock passing through the pulse generating circuit 201 is a pulse and inputted to the latch circuit 200 as the clock signal. When the pulse as the clock rises, the latch circuit 200 fetches a data D from a terminal 15 and outputs a data after a time tpd0 being a pass through time of the latch circuit 200, the output waveform of the latch circuit 200 is maintained to execute flip-flop operation. Thus, the latch circuit 200 is surely operated. COPYRIGHT: (C)1991,JPO&Japio

Scan path generation with flip-flop rearrangement according to geometry of logic circuit

Abstract: In a scan path generation system, flip-flops and logic elements of a logic circuit are placed on an X-Y plane according to logical connection data and original scan path data. Data describing a sequence in which the flip-flops are to be arranged for the benefit of the geometry of the logic circuit is prepared and stored in a sequence table. The flip-flops on the X-Y plane are rearranged according to the data stored in the sequence table. New scan path data is derived from the rearranged flip-flops and are substituted for the original scan path data to be used for connecting the flip-flops. Due to the rearrangement process, the flip-flops can be connected in a scan path with relatively short and straight path sections between successive flip-flops, minimizing the amount of channel space which is occupied by the scan path.

Application of logic cell arrays in design of self-clocked sequential circuits

Abstract: A systematic method of design for asynchronous sequential circuits using logic cell arrays such as the XILINX 2000 or 3000 series is presented. In this method each state is represented by a separate flip-flop whose clock signal is generated locally. State machines of considerable size can be accommodated on a single chip and in most applications the outputs are readily available on the chip without the need for external decoding of the states. Problems of races and hazards, commonly associated with asynchronous circuits, are eliminated. The method is applied to the design of a VME bus requester, and the use of CAD packages to simulate such designs is discussed. >

Multiplex signal separation circuit

Abstract: PURPOSE:To attain a high speed operation and to increase a phase margin by using a D type flip flop which latches a multiplexed input signal by means of the rise of a clock signal and the D type flip flop which latches it by means of the fall of the clock signal. CONSTITUTION:The first D type flip flop 11 fetches input data IN by the rise of the clock signal having half the clock rate of the data rate. The second D type flip flop 12 fetches input data IN by the fall of the clock signal CK, namely, the rise of the inverse of the clock signal CK. Since the multiplexed input signal is alternately divided by the rise and fall of the clock signal having the half clock rate of the data rate, the D type flip flops 11 and 12 to be used need to move at the frequency half the data rate. Thus, a demultiplexer having the high speed data rate can easily be obtained.

Frequency dividing circuit

Abstract: PURPOSE:To form a frequency-dividing circuit having a frequency-dividing ratio which is 1/(n+0.5) by forming a 1/2 frequency-dividing circuit by the output signal of the frequency-dividing circuit composed of an edge trigger type FF or a signal equal to it, and controlling the polarity inversion action of an exclusive 'or' circuit. CONSTITUTION:An FF1 or FF3 constitutes an edge trigger type flip flop circuit and an FF1 and an FF2 constitutes the frequency-dividing circuit having a 1/3 frequency-dividing ratio. The FF3 constitutes a 1/2 frequency-dividing circuit. A frequency-dividing input pulse CP is supplied to one side input of an exclusive 'or' circuit EX1 as a polarity inverting circuit and a non-inverting output Q of the FF3 is supplied to other input. The exclusive 'or' circuit EX1, when the level of both input signals is coincident, forms the output signal of the low level. Thus, the frequency-dividing action of 1/2.5 can be performed.

High speed cmos flip-flop employing clocked tristate inverters

Abstract: A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel data paths from the data input terminals to Q and Q/ output terminals. The improved circuit design realizes higher operating speed than prior CMOS flip-flops by eliminating the inverter delays present in single path flip-flops and providing only two gates in the data paths between the input and output terminals.

Delay type flip-flop arrangement using transistor transistor logic

Abstract: A flip-flop arrangement receiving a clock signal and an input data and outputting a logical output in accordance with a logical level of the data. The arrangement includes a master flip-flop for transmitting a change in the logical level of the data to a pair of output ends when the clock signal is at a predetermined logical level; a slave flip-flop for latching the data transmitted via the pair of output ends; an output buffer for effecting a buffering of the data latched in the slave flip-flop; and a drive circuit for driving the output buffer. The drive circuit responds to logical levels of data appearing at the pair of output ends of the master flip-flop and, based on the logical levels, drives the output buffer to determine a logical output to be output from the arrangement, thereby reducing a total propagation delay time and realizing a high speed operation without increasing a power dissipation.

Flip-flop circuit

Abstract: PURPOSE:To obtain an FF circuit able to prevent malfunction and implement stable FF operation by using an edge of a data change point so as to invalidate a clock signal if a data and a clock is in contention with each other. CONSTITUTION:A data signal D1 is inputted to a clock input CK of two FFs 2, 3 provided newly in in-phase and opposite phase. Q outputs of each are ANDed by an AND circuit 7 and given to its own reset terminal R. An AND circuit 8 ANDs an AND output of the circuit 7 and an existing clock signal and its resulting AND output is given to a clock input CK of the existing FF1. Then an FF4 is provided newly to avoid double clocks to invalidate a pulse for nearly a half period of a clock when one clock pulse comes. Through the constitution above, malfunction is prevented by invalidating a clock signal by using an edge of a data change point if a data and a clock are competed.

Multifunction scan flip-flop

Abstract: PURPOSE: To enable reliable verification of timing of a synchronous logic circuit by providing a control means of delaying either one of data and a clock relatively from the other. CONSTITUTION: A data input DI is given to a selection circuit 2 through a delay circuit 1 or directly. The selection circuit 2 selects either of two signals thus obtained and gives it to a data input D of DFF 5. Meanwhile, a clock input CKI is given to a selection circuit 4 through a delay circuit 3 or directly. The selection circuit 4 selects either of two inputs and gives it to a clock input CK of the DFF 5. A data output Q of the DFF 5 is fetched as a data output Q 0 . Moreover, a signal C2 and a signal C1 are given as control signals to the selection circuit 2 and the selection circuit 4 respectively. According to this constitution, verification of the degree of allowance of timing of a data hold time is enabled and the verification of the timing can be executed simply. COPYRIGHT: (C)1992,JPO&Japio

D flip-flop circuit

Abstract: PURPOSE:To test in a short time without consecutive application of clocks by controlling D FP transfer gates in tandem connection with a prescribed signal formed from a clock and a test signal at the test. CONSTITUTION:A clock 10 and a test signal 9 via an inverter 11 are processed by a NAND gate 12, signals CNB 16, CPB 18 controlling a D FF gate 1 of a master section 5 are generated similarly by NOR processing and signals CP 17, CN 10 controlling a D FF gate 3 of a slave section 6 by the clock 10 and the signal 9 are generated. Then a P-channel gate 1 and an N-channel gate are closed thereby conducting the test of D FF gates in tandem connection of the master-slave system not by a consecutive clock but by a single clock quickly.

Bidirectional buffer circuit

Abstract: PURPOSE:To obviate the signal line of a direction control signal and to simplify the circuit by providing a means to generate the direction control signal in accordance with a driven signal. CONSTITUTION:Based on input signals of a first buffer 3a and a second buffer 3b, a generating means (for example, a flip flop) 4 generates the direction control signal which validates one of first and second buffers 3a and 3b, namely, the direction control signal which validates the buffer to which the driven input signal is first inputted. That is, direction control signals (c) and (d) are generated in accordance with driven signals by first and second buffers 3a and 3b. Thus, it is sufficient if only driven signals are given to the bidirectional buffer circuit, and the generating means 4 consists of two gates 41 and 42, and therefore, the circuit constitution is simplified.

Multifunctional flip-flop circuit

Abstract: PURPOSE: To make it possible to be operated as a D flip flop, level sensitive latch or simple flow through device by providing respective input terminals for data, preset, clear and clock, and a data output terminal. CONSTITUTION: This circuit is provided with data, preset, clear, and clock input terminals D, and a data output terminal Q. Then, when one or both of preset P and clear C signals are 1, a flip flop 123 operates like a D flip flop, and when the both P and C signals are 0, the flip flop 123 operates like a flow through device. Also, the flip flop 123 can operate as a level sensitive latch by latching flow through data when a CLK is turned into a low state. Thus, this circuit can operate as the D flip flop, flow through device, or level sensitive latch.

Circuitry ascertaining start of switch-over time - connects outputs of two OR=gates and via AND=gate for star points of antiparallel thyristor bridges of rectifier or inverter

Abstract: An inverter circuit for supply of electrical motors has a thyristor based bridge network (2) arranged in two groups (GR1, GR2). Opto-couplers provide signals to a circuit that allows determination of the start of the switching period. The opto-couplers connect Cu a pair of logic inverters (3,41) providing inputs to a logic circuit (8,10,14,15) supplied by a flip flop (7) set and reset by OR-gate signals (4,6). The OR-gates respond to the firing signals applied to the thyristors. The output gate (15) signals the start of the switching period. ADVANTAGE - Fastest possible switchover is surely detected currentless state.

Logic circuit having flip-flop function

Abstract: A logic circuit comprises a first terminal (D, D , 102a, 102b) for receiving an input data signal (D, D ), a second terminal (C, 106) for receiving a clock signal (C, CLK*), a first latch circuit (32, 121-123) coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit (33, 124, 125) coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal (Q, Q , 103a, 103b) for outputting an output data signal (Q, Q ) which is output from the second latch circuit, and a selecting part (30, 104, 121, 122) coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode.

Variable frequency divider

Abstract: PURPOSE:To always make constant the synchronous time of a phase locked loop(PLL) by holding a latch enable(LE) signal by means of a flip flop(F/F) circuit, obtaining the synchronization with a reference frequency dividing signal, and transmitting it. CONSTITUTION:For the LE signal inserted fro an LE input terminal 3, the synchronization with a latch selective signal 20 of frequency dividing data in a shift register is obtained in an AND circuit 9, and it is held by an F/F circuit 22. After the coincidence with a reference frequency dividing signal 18 is obtained by an AND circuit 21, it is delayed by a delay circuit 23, and transmitted to a latch circuit 14 and an F/F circuit 25. Further, by the signal from a reset signal input terminal 24, the F/F circuit 25 is reset. Thus, the phase locked time of the PLL circuit can be always made constant.

Flip-flop circuit device

Abstract: PURPOSE:To reduce the number of elements by providing a P-channel MOS transistor which fixes the state of a bidirectional transfer gate circuit at the time of setting as setting an FF circuit device without having a set function as a base, and adding a set circuit at a master side FF circuit. CONSTITUTION:A CMOS type FF circuit device is provided with the P-channel MOS transistor 5 which sets a source voltage terminal VDD as the source in a master side FF circuit 30 in which a set circuit is provided, and is comprised of a slave side FF circuit 31 without having the set circuit. The bidirectional transfer gate circuits 1 and 4 are turned off, and the bidirectional transfer gate circuits 2 and 3 are turned on. The master side FF circuit 30 is set at a holding state, and the P-channel MOS transistor 5 which inputs the inversion signal of a set signal is turned on, therefore, the output Q of the FF circuit device is held at the high level, which enables the FF circuit device to be set. In such a way, the number of elements can be reduced, and the reduction of an LSI chip can be realized.

High side driver mos circuit

Abstract: PURPOSE: To reduce power consumption by driving a flip flop(FF) by two pulse signals induced from a driving switching signal through respective SET and RESET terminals. CONSTITUTION: The circuit is driven through the gate of a power switching transistor(TR) M1. Load elements Rp1 , Rp2 are respectively connected between the drains of two input TRs M2S, M2R and a node VGG. When the TRs M2S, M2R are OFF states, the drain potential of the TRs M2S, M2R is held at a level corresponding to a steady logic state '1'. The TRs M2R, M2S are respectively driven by two pulse signals CR, CS. Since substantial current lead-in due to a driving circuit is generated only for a transition state, power consumption can be reduced.

Circuit arrangement for receiving serially transmitted digital data

Abstract: The object is to be able to use a control clock which is asynchronous to the data stream in the reception of data arriving serially. The incoming data bits are sampled with a sampling and counting clock, which is asynchronous to the data stream, at an approximately integral multiple of the bit rate but at least three times, and transferred into a shift register. The outputs of the shift register are connected to an evaluating logic which influences a counter controlled by the same clock, with the same number of counting steps as there are stages in the shift register, in such a manner that a control clock appears at one of its outputs. This is used for clocking a D-type flip flop which accepts the data from another output of the evaluating logic. Due to the asynchronous sampling and counting clock, no phase detector circuits are necessary and no high requirements for the frequency accuracy of the clock generator are necessary. The entire circuit arrangement can be combined in one integrated circuit so that the higher frequencies do not appear at the inputs and outputs of this circuit.

D flip-flop circuit

Abstract: PURPOSE:To attain the operation at a high speed with a single phase clock signal by providing a gate section passing a signal stored in a memory cell section when a transfer gate section is closed and an RS flip-flop section varying the state of an output signal with the signal from the gate section. CONSTITUTION:A D flip-flop circuit consists of enhancement field effect transistors(TRs) 1A, 1B, a memory cell 2 provided with inverters 2A, 2B, two- input NOR circuits 3A, 3B and an RS flip-flop 4 provided with two-input NOR circuits 4A, B. When the transfer gate sections 1A, 1B are closed based on the clock signal in this case, the gate sections 3A, 3B are opened based on the clock signal and the signal stored in the memory section 2 is inputted to the RS flip-flop sections 4A, 4B via the gate sections 3A, 3B. Thus, the D flip- flop circuit is operated with a single phase clock.