Showing papers on "Flip-flop published in 1993"

Path delay fault simulation of sequential circuits

Abstract: To analyze path delay faults in synchronous sequential circuits, stimuli are simulated in a dual-vector mode. The signal states represent the logic and transition conditions for two consecutive vectors. After the simulation of each vector, only the activated paths are traced and the corresponding fault effect, if propagated to a flip-flop, is added to its fault list. A path numbering scheme avoids storage of path data which can be generated, if needed, from the path number. The simulation is independent of the specific delays of the combinational elements, and either robust or nonrobust detection can be simulated as options to the user. For robust simulation, an update rule for state variables is proposed whereby a flip-flop is updated with its correct value, provided it is a destination of at least one robustly activated path. This rule gives a higher and more realistic coverage of robustly detected faults. Experimental results verify the effectiveness of the simulator. >

Superconducting flux flow digital circuits

Abstract: A family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins is presented. The circuits are made from high-temperature superconductors (HTSs) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40 ps when using 3- mu m linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic. >

Bistable flip-flop with reset control

Abstract: A bistable flip-flop with reset control is provided. The flip-flop includes a storage cell having a first inverter whose input can receive a write signal from an input signal delivered to the input terminal of the first inverter, and a second inverter which is feedback-mounted with respect to the first inverter. The flip-flop also includes a first switch controlled by a reset signal for enforcing a specified logic state at the input of the first inverter when the reset signal is active, and a second switch controlled by the reset signal so as to prevent the first inverter from receiving a write signal in a logic state opposite to the specified state when the reset signal is active.

Testing of resistive bridging faults in CMOS flip-flop

Abstract: This paper provides an analysis of flip-flop testability with respect to resistive bridging faults. Problems inherent to their detection not encountered in combinational circuits are discussed, and practical solutions are proposed to overcome the main difficulties. >

Flip flop circuit and method therefor

Abstract: A storage cell circuit (11) comprises a voltage reduction circuit (17), a latch (18), and a tri-state driver circuit (19). The latch (18) has a terminal (14) and a terminal (16) for providing data stored therein. The voltage reduction circuit (17) couples to the power terminal of the latch (18) and reduces the voltage powering the latch. The tri-state driver circuit (19) has a clock input (12), a data input (13), a terminal coupled to the terminal (14), and a terminal coupled to the terminal (16). A clock signal applied to the clock input (12) has a first phase and a second phase. During the first phase of the clock, the terminals of the tri-state driver circuit (19) are at a high impedance leaving the data stored in the latch (18) undisturbed. During the second phase of the clock, the tri-state driver circuit (19) provides complementary signals of a data signal applied to the data input (13) for writing to the latch (18).

Transparent flip-flop

Abstract: An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.

Asynchronous or synchronous load multifunction flip-flop

Abstract: According to the present invention hardware is provided in a user configurable logic integrated circuit chip to allow a user to select multiple storage functions such as D, T, JK, to receive multiple input signals and generate a storage input signal using a function such as OR or MUX, along with parallel load and asynchronous load options. A relatively small hardware area can offer these functions, which are commonly used, and can leave general purpose logic for other more complex functions, thus increasing the amount of logic which a user may implement in a given silicon area.

Latch circuit and master slave type flip-flop circuit

Abstract: PURPOSE:To obtain the latch circuit by which a high processing speed and low power consumption are attained. CONSTITUTION:A switching means 22 is conductive and input information is delivered to a node 3. In this case, a switching means 22 is conductive and the node 3 and a node 18 are electrically connected. When current input information is inverted preceding input information, a potential of the node 3 is quickly changed by the inverted information stored in a capacitive element 17 and the information based on the current input information is outputted to an output node 2. When a switching means 5 changes to the nonconductive state, the switching means 22 changes to the nonconducting state and the node 3 receives no effect of the capacitive element 17. In this case, the switching means 12 is conductive and the information of the node 11 is delivered to a latch section input node 3, a latch section 8 reaches the latch state, a switching means 19 is conductive and the information of the latch section output node 4 is delivered to the node 18 via the switching means 19 and the inverted information is stored in the capacitive element 17.

D flip-flop circuit

Abstract: PURPOSE:To provide the D flip-flop used to form a shift register surely latching a signal independently of the presence of skew in a clock signal. CONSTITUTION:A switch SW1 is closed with a clock CK set to a low level and an input signal D is latched by a latch circuit comprising inverters 3, 4. With the clock CK set to a high level, a switch SW2 is closed and an output of the inverter 3 is latched by a latch circuit comprising inverters 7, 8. An output of the inverter 7 is fed via a resistor R to an inverter 9, where it is inverted and further inverted by an inverter 10 and the result is outputted externally. The input signal to the inverter 9 is delayed sufficiently from the clock outputted from an inverter 12 by the action of the resistance. R and the capacitance of the input section of the inverter 9, then no latch mistake takes place due to a skew in the clock signal in the shift register comprising lots of connection of the D flip-flop circuits as above.

A 20-Gb/s flip-flop circuit using direct-coupled FET logic

Abstract: A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFL's advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2- mu m-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well. >

Automatic clock adjustment circuit for IC(s) with D type flip=flops for data acceptance - synchronises data inputs to clock signal by delaying clock signal w.r.t. gate rise-fall and flip=flop transition-set times

Abstract: The adjustment circuit has a D type flip-flop reset input connected to the output of a multiplexer (2) whose inputs receive clock signals delayed by a gate transition time. The flip-flop set output is connected to one input of an Exclusive-OR gate (3) whose second input receives data via a timing element (4) with delay equal to the sum of the set time and the flip-flop transition time. The Exclusive-OR output is connected to the input of a counter whose outputs are connected to the control inputs of a multiplexer. USE/ADVANTAGE - Automatic synchronising of clocking signals for IC with D type flip-flops for data acceptance.

D type flip-flop

Abstract: PURPOSE:To reduce the unnecessary electric power of a D type flip-flop during the operation of an input latching signal. CONSTITUTION:The EXOR is secured between a data input signal (d) and an output signal Q for a master latch 31, a slave latch 30, and a D type latch 32. When the values of signals (d) and Q are different, the latch 32 works as a D type flip-flop after an input latching signal C is directly transmitted to a CK and an inverse of CK respectively. When both signals (d) and Q are equal to each other, the latch 32 is latched. In such a constitution, the power consumption of the flip-flop can be reduced.

Logic integrated circuit device and its manufacture

Abstract: PURPOSE:To modify a circuit in a short time on the basis of the results of functional tests by wiring part of circuit elements for a scan circuit as the circuit element of a functional circuit. CONSTITUTION:A scan circuit 10 is provided for performing functional tests on the circuit section of a functional circuit 1 incorporating a flip flop(FF) 2 and NAND circuit 3 and contains four AND circuits 13-16, two NOR circuits 17 and 18, and four inverters 19-22 in addition to D flip flops 11 and 12. A gate 4 is connected to a net A between an input node (a) through which signals are inputted from the functional circuit 1 to the scan circuit 10 and an output node (b) through which test signals are outputted from the scan circuit 10 to the functional circuit 1 and the circuits can be disconnected from each other from the said section through the gate 4 at the time of functional tests. In case some trouble is bound in the circuit section of the functional circuit 1 as a result of a functional test, part of the circuit elements contained in the scan circuit 10 is utilized as required.

Flip-flop circuit

Abstract: PURPOSE:To improve the reliability of a combinational logical circuit to be tested by enabling the inspection of a set/reset signal at the time of performing a scan pass test. CONSTITUTION:At the time of performing a scan pass test, multiplexers M11 and M12 supply a set signal I16 to be supplied from a combinational circuit L1 to data terminals D1, D2 of primitive flip-flop circuits PF11, PF12 in response to control signals I14, I15, I24 and I25, and enables the signal to be read as data. Thus, as the abnormality of the set signal caused by the fault of the combinational logical circuit can be detected, the fault detection rate of a combinational logical circuit can be improved.

Set reset flip-flop circuit

Abstract: PURPOSE:To reduce the area of the circuit and to decrease the increase in the area when its drive capability is improved by providing a circuit taking preceding a set signal over other signal and a latch circuit comprising plural inverters to the flip-flop circuit so as to reduce the number of transistors(TRs). CONSTITUTION:The circuit is provided with a set priority circuit 1A for a single output taking precedence a set signal over other signals and with a latch circuit 1B comprising plural inverters 14, 15 receiving the output signal of the set priority circuit 1A. The set priority circuit 1A is a set priority flip-flop (S-RFF) and consists of P-channel TRs 11, 13 and an N-channel TR 12. The inverter 14 consists of a P-channel TR 141 and an N-channel TR 142 and the inverter 15 consists of a P-channel TR 151 and an N-channel TR 152. Thus, the area is reduced by decreasing the number of the TRs and the flip-flop circuit whose area increase is less is realized when the drive capability is improved.

Flip-flop circuit for controllable copying between slave latch and scanning latch

Abstract: PURPOSE: To reduce the power consumption by providing a master latch circuit, a slave latch, a scanning latch circuit, and a copying circuit in which one of the slave latch and the scanning latch receives and latches a signal from the other one. CONSTITUTION: Inverters I3, I5, I7 in respective latches have stronger driving ability than that of I4, I6, I8. Thereby, an output of a latch can drive an input of a next latch independently of a next inverter having a weak latch. When a slave latch 14A has a high output value, input of the I6 is made high and its output is made low. An output of the I6 drives an input of the I5, an output of the I5, that is, a value in the latch 14A is kept at a high value. When it is desired that a value in the latch 14A is changed to a low value, an output of the I3 in a master latch 12A is set to a high value, a control signal DCLK is affirmed, a bus/transistor T4 can be used. Consequently, a bus/transistor T5 can be used.

D flip-flop circuit

Abstract: PURPOSE:To mount a multi-stage counter or a register circuit with a set or reset terminal having a small area into an integrated circuit chip by fixing an output in the initial state with small number of transistors (TRs). CONSTITUTION:Transmission gates 6, 9, 11, 14 in the inside of the flip-flop circuit are all turned off by setting clock signals CLK(1), CLK(2)3 to be in phase, e.g. setting a high level to both the clock signals. In this state, N-channel TRs 10, 15 are turned on by setting a level of a line ENB4 to a high level, and a master side output (output of inverter 7) and a slave side output Q18 are respectively fixed to a high level and a low level. Then the level of the line ENB4 is set to a low level to turn off the N-channel TRs 10, 15 and when the clock signal CLK(2)3 is set to a low level, the transmission gates 6, 14 are turned on and a Q output 18 of the flip-flop is kept to be a low level and a clock of an inverted phase is inputted as the CLK(2)3.

High-speed path gate, latch and flip-flop circuit

Abstract: PURPOSE: To decrease a data signal propagation time started at the detection of a clock signal to a final output data signal, to increase a switching transition speed at a final output terminal and to increase an output drive current. CONSTITUTION: A BOCMOS pass gate circuit PSGT 3 used for a latch circuit and a flip-flop circuit integrates a bipolar pull-up transistor(TR) Q1 and a bipolar pull-down TR Q3 to charge a load capacitance CL transiently. A bipolar output circuit replies a data signal at a path gate input terminal V'IN in the transparent operation mode to provide a sink and source output drive current amplified by β at a pass gate output terminal VOUT. Transistors(TRs) QP3 , QP4 , QP5 , QP6 and a NAND 1 of a MOS input logic circuit control TRs Q1, Q3. An output latch back circuit LTBK 2 latches an output data signal.

Master-slave flip-flop with controllable copying between slave and scan latches

Abstract: A scannable MSFF 10 allows data at its data or scan inputs to be stored in the slave 14 or shifted out of the flip-flop at its scan output. Data stored in the slave 14 may also be shifted out at the scan output, without losing slave 14 data. The latches may be constructed from CMOS inverters and transmission gates.

Flip-flop circuit

Abstract: PURPOSE:To prevent malfunction of a shift register by delaying a timing setting a slave latch to the through-state more than a timing setting a master latch to the latch-state at a leading edge of a clock signal. CONSTITUTION:A delay circuit delaying only a leading edge of a clock input CLK consists of a delay circuit 4 and an AND circuit 5. Furthermore, a flip-flop circuit 6 is formed of a master latch 1 made up of an inverter 3 and a latch 1 and a slave latch 2 connecting an output terminal of the delay circuit to a gate input terminal. Thus, the timing setting the slave latch 2 to the through- state is delayed more than a timing setting the master latch 1 to the latch-state to prevent malfunction of the shift register due to a metal skew.

Horizontal phase correcting circuit

Abstract: PURPOSE:To decrease the number of circuit elements and to perform IC processing by locking a second AFC loop circuit by the output pulse signal of a deciding circuit when a digital signal value correspoding to the correction data and the output signal value of a counter are matched. CONSTITUTION:When a DSP 10 and the output signal of a counter 20 are matched, a second AFC loop circuit is locked by a pulse signal outputted from a flip flop 50, and thus, since the horizontal output is phase-modulated, a D/A converter becomes unnecessary, and even at a phase converting part, the phase modulation by an analog circuit becomes unnecssay. Then, the number of elements used for a circuit can be decreased, the IC processing of the circuit is facilitated, and the cost can be decreased. Since the digital signal of the DSP 10 is converted to the phase correction as it is, the dispersion of the phase is eliminated, and the correction accuracy by the temperature characteristic can be improved.

Electronic type flip-flop circuit

Abstract: PURPOSE: To prevent the circuit from responding to a slow clock ridge and clock skew by allowing a 2nd transfer gate to delay a transfer time of data from a 1st storage element to a 2nd storage element. CONSTITUTION: A transistor(TR) 13 acts like a diode that responds to a ridge rising toward a positive level of a clock signal to block increase in a voltage at an input terminal 16 of a slave block. Since the clock signal drives simultaneously both transfer gates similarly to the case with that for an FF circuit, occurrence of a transparent state of the FF circuit is partially cancelled. However, since only on TR is not employed for a 2nd transfer gate different from the FF circuit but the transfer is attained via an inverting element consisting of TRs 10, 11, there is some delay in the transfer from a master block to the slave block in the FF circuit. Even in the case that a short time state when both TRs 4, 12 are turned on is caused in the FF circuit, data at an input terminal are not immediately transferred to an output terminal.

Interruption control circuit

Abstract: PURPOSE:To execute an interruption processing in an interrupted order even if plural interruption signals are inputted to CPU with less interrupting terminals. CONSTITUTION:Two interruption inputs INT0 and INT1 are bundled into one by an OR circuit 21, and a one-shot multivibrator 22 extends it to the pulse of width which CPU can recognize, whereby it is inputted to the interruption terminal of CPU 30. The interruption signals are stored in flip flops 3 and 4 being registers, The information are written from the flip flops 3 and 4 into the flip flops 5 and 6 only when the flip flops 6 and 5 being flag registers showing the occurring place of interruption are respectively not set by the control of NAND gates 7 and 8. A bit reset signal which CPU receiving interruption discrimination information outputs is controlled by the NAND gates 9 and 10 and only the flip flop which is set at present is reset.

Master/slave type flip flop circuit

Abstract: PURPOSE: To quickly switch from the latch operation to the signal take-in operation by setting a current for signal take-in to a value larger than a current for latch use. CONSTITUTION: A current IX for signal transmission use and a current IY for latch use set by FET TX and TY are set to satisfy IX>IY. Consequently, a relation between source currents IM 2 and IS 2 which are turned on at the time of take-in signal of FETs M 2 and S 2 and source currents IM 3 and IS 3 which are turned on at the time of latching signals of FETs M 3 and S 3 becomes IM 2 >IM 3 and IS 2 >IS 3 . Therefore, driving capabilities of FETs M 2 , M 4 , and M 5 in a master filp flop circuit A are higher than those of FETs M 3 , M 6 , and M 7 , and the latch state is quickly switched to the state that complementary input signals D and DB can be taken in. In a master flip flop circuit B, driving capabilities of FETs S 2 , S 4 , and S 5 are higher than those of FETs S 3 , S 6 , and S 7 in the same manner, and the latch state is quickly switched to the state that state signals of contacts PM 1 and PM 2 can be taken in. COPYRIGHT: (C)1994,JPO&Japio

Flip-flop circuit

Abstract: PURPOSE:To obtain a flip-flop circuit, which facilitates the diagnosis of a combination circuit, has a set/reset function and make clock skew management easy by controlling a first latch circuit in response to a clock signal for diagnosis at the time of diagnosis operation CONSTITUTION:Main data are given to a first latch circuit L1 and held therein in response to a clock signal for diagnosis when a control signal is set at a first state at the time of diagnosis operation At this time, since a second clock signal is not given to a second latch circuit L2, data within the second latch circuit L2 are held When the control signal is set at a second state, a set/reset signal is given to the first latch circuit L1 in response to the clock signal for the diagnosis Thereby the first and the second circuits L1, L2 are set or rat The output signal of the first latch circuit L1 are given to the second latch circuit L2 and held therein in response to another clock signal for second shift operation at the time of shift operation

Processor responsive to environmental conditions to enable or disable a delay in a processing action

Abstract: A processor includes logic circuitry (30) for producing output signals in response to input signal states from other circuitry (31), such input signal states subject to signal delays resulting from environmental conditions. The processor includes a wait state circuit (36) connected to the logic circuitry (30) for delaying operation of the logic circuitry (30) in response to the input signal states for a time period, the time period set in accordance with a worst case propagation delay of signals that give rise to the input states. A delay circuit (38) is responsive to environmental conditions for providing a delay indication if signal delays that result from the environmental conditions are less than a predetermined value. Further circuitry (40) is responsive to the delay indication to disable the wait state circuitry (36) so that the logic circuitry (30) operates in a more rapid manner. In one embodiment, the delay circuit (38) comprises a chain of circuits which feeds an edge triggered flip flop (40). In another embodiment, the delay circuit comprises a ring oscillator (70) whose output is compared with a known frequency (76) as a measure of signal propagation speed.

Flip-flop circuit

Abstract: PURPOSE:To normally operate a shift register even when a delay in the wire gives an effect onto a gate array and its timing is deviated. CONSTITUTION:A 4-1 multiplexer 2 is connected to the data input of a flip-flop 3. After automatic arrangement and wiring, a stray capacitance of wiring and a wiring resistance are decided and whether or not a shift register is normally in operation is discriminated from the capacitance and the resistance. When the shift register is not normally in operation, inputs A, B of a flip-flop circuit 5 are controlled to avoid it by matching the delay time of an optimum delay time.

Serial/parallel conversion circuit

Abstract: PURPOSE:To provide a serial/parallel conversion circuit reduced at the number of gate circuits required for its constitution. CONSTITUTION:Each of register blocks F00 to F33 is constituted of an R-S flip flop(FF) consisting of plural NAND gates G2, G3 and a NAND gate G1 for selecting the R-S FF. Each of decoders G4, G5 selects one register block out of the blocks F00 to F33 based on the integration value of serial clocks inputted by a counter K1 and sets up data inputted from a data input terminal D in the selected register block.

Flip-flop circuit

Abstract: PURPOSE:To obtain a flip-flop circuit in which an input load is made constant without increasing the number of components CONSTITUTION:Switches 3, 8 or switches 4, 6 are set to ON state or OFF state based on a clock input signal and inverters 7, 9 or 5, 7 are brought into a latch state alternately or the latch state is released Thus, a data input signal DIN is fetched at the rise of the clock input signal and the fetched data are latched when the clock input signal is in the other states