Showing papers on "Flip-flop published in 1996"

Flow-through latch and edge-triggered flip-flop hybrid elements

Abstract: This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.

Apparatus for scannable D-flip-flop which scans test data independent of the system clock

Abstract: The present invention discloses an apparatus for controlling and observing test data stored in scannable-D-flip-flops independent of a system clock, thereby making the scannable-D-flip-flops well suited for partial scanning Design-For-Test (DFT) techniques. Under the present invention, the scannable-D-flip-flop is comprised of two master latches and one slave latch such that the scannable-D-flip-flops may operate in a normal mode of operation or a scan/test mode of operation. During normal mode of operation, the first master latch operates together with the slave latch in response to the system clock. During the scan/test mode of operation, the second master latch operates together with the slave latch in response to a scan clock. Since the scanning of external test data is controlled by the scan clock, the conventional non-scannable D-flip-flops in the design, which are controlled by the system clock, maintain their previous states during a scanning operation. Also disclosed is a method for performance testing integrated circuits utilizing the scanning application of the scannable-D-flip-flops. This is accomplished by constructing a test circuit that spans the entire silicon die area. By using a special AC-TEST-MODE control signal, the scannable D-flip-flops are set to a "flow-through" mode to provide a direct path through the scannable flip-flops such that the test circuit forms an oscillator in which the frequency of the device can be measured.

Clock skew optimization for peak current reduction

Abstract: The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced by more than a factor of two without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern.

Flip-flop circuit, scan path and storage circuit

Abstract: In order to obtain a flip-flop circuit which reduces an S/H time or a T-Q delay while suppressing power consumption, a master latch is formed by a dynamic half latch having a transmission gate (S1) and an invertor (INV1), while a slave latch is formed by a static half latch having transmission gates (S3, S4) and invertors (INV3, INV4). In the slave latch, the operation of the transmission gate (S4) is controlled not only by a clock signal (T) but by a mode signal (MODE). When the mode signal (MODE) is converted to a low level, the transmission gate (S4) enters a nonconducting state, so that the slave latch performs a dynamic operation.

Partial scan design based on circuit state information

Abstract: State information of a sequential circuit can be used to evaluate the complexity of test generation. The ratio of valid states to all the states of the circuit is an important indicator of test generation complexity. Using valid states obtained via logic simulation, a testability measure based on the density of encoding is proposed for scan flip flop selection. A second testability measure based on the test generation state information is also presented and used to select scan flip flops. Cycles are broken selectively on the basis of the circuit state information. Good fault coverage and test efficiency are obtained when fewer scan flip flops than the minimum cut set are selected. Experimental results are presented to demonstrate the effectiveness of the method.

Flip-flop with full scan capability

Abstract: A flip-flop with scan capability includes a four switches, a master stage, a slave stage and a scan-out logic gate. The flip-flop can operate in a functional mode, and a scan mode and receives a clock signal, a data signal, a scan clock signal and a scan-in signal. The flip-flop enters the functional mode when the clock signal runs free and the scan clock signal is held constant. The first switch receives the data signal and provides the data signal to the master stage for storage during a first part of a clock cycle. During a second part of the clock cycle, the third switch, connected between the master stage and the slave stage, closes, providing the data stored in the master stage to the slave stage and outputted as a q output signal. The flip-flop enters the scan mode when the clock signal is held constant and the scan clock signal runs free. The first switch is controlled to stay open by the constant clock signal. During a first part of a scan clock cycle, the second switch closes, providing the scan-in signal to the master stage. The data stored in the master stage is provided to the fourth switch, connected between the master stage and the scan-out logic gate. During a second part of the scan clock cycle, the fourth switch closes, providing the data stored in the master stage to the scan-out logic gate, which outputs a scan-out signal.

Single phase edge-triggered dual-rail dynamic flip-flop

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard a n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.

Edge-triggered dual-rail dynamic flip-flop with self-shut-off mechanism

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data put signal. The first and second input latches have first and second shutoff circuits, respectively. During a precharge phase, the first and second input latches each provide an output signal of a first logic level. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal, respectively. In response to the samples of true and the complement of the data input signal, one input latch's output signal will transition to a second logic level, while the other input latch's output signal will remain at the first logic level. A first output latch and a second output latch are coupled to receive the output signals of the first and second input latches, respectively. The first and second output latches are inverting. During the precharge phase, the flip-flop provides output signals of the second logic level from both of the output latches. During the evaluation phase, one output latch will continue to provide an output signal of the second logic level and the other output latch will provide an output signal that transitions from the second logic level to the first logic level.

Zero setup time flip flop

Abstract: Circuits and methods for a zero setup time storage element are disclosed. A storage element having a data input terminal, a clock input terminal and a data output terminal is able to capture a logic value of a data signal on the data input terminal with a substantially zero setup time at an active edge of a clock signal. Furthermore, some embodiments of the storage element are able to drive the captured logic value until the next active edge. One embodiment of the storage element includes a control circuit coupled to an output driver circuit. Depending on the state of the data input signal during an active edge, the control circuit can drives a first control signal to the output driver circuit or a second control signal to the output driver circuit. The output driver drives a data output signal on the data output terminal of the storage element based on the values of the control signals.

Dual edge D flip flop

Abstract: An integrated circuit provides for doubled data throughput by clocking data on both edges of an attached clock signal. The circuit includes an upper latch stack, responsive to the clock rising edge, and a lower latch stack responsive to the clock falling edge, each latch stack outputting a respective set and clear signal. An active overlap filter logically ORs the set and clear signals from the upper and lower latch stacks to a third set and clear signal which controls operation of an output latch. Data lines are connected to the upper and lower latch stacks, such that a first data signal is clocked to the circuit output during a clock rising edge transition and a second data signal is clocked to the output during a clock falling edge transition. Filter circuitry between the latch stacks and the output latch ensures that set and clear are not asserted simultaneously, thus providing for "glitch" free operation of the circuit.

Noise insensitive high performance energy efficient push pull isolation flip-flop circuits

Abstract: An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ N-type MOSFETS, CMOS transfer gates or tri-state inverters in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.

Complementary Digital Logic Using Resistively Coupled Single-Electron Transistor

Abstract: A new complementary digital logic based on resistively coupled single-electron transistors (R-SET) was proposed and its basic characteristics were numerically analyzed using the Monte Carlo method. The proposed logic has a logic threshold independent of background polarization charges which induce crucial problems in logic operation in the case of a capacitively coupled logic. In addition, the proposed complementary R-SET logic has larger output voltage swing and better logic level stability than those of a conventional resistance-load R-SET logic. The stability of the logic level of the complementary R-SET logic was investigated by calculating the data retention time of flip-flop circuits, and its dependence on temperature and shot noise was examined. For stable operation of the flip-flop circuit, estimated optimal operation temperature and switching delay time are e 2 /80C t k B and 1500 R t C t , respectively, where C t and R t are capacitance and resistance of the tunnel junction.

Mos master-slave flip-flop with reduced number of pass gates

Abstract: A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances IDDQ- testability with respect to known flip-flops.

A super-dynamic flip-flop circuit for broadband applications up to 24 Gbit/s utilizing production-level 0.2-/spl mu/m GaAs MESFETs

Abstract: This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wide-band clock buffer is introduced to cover the FF operation range. An 8- to 24-Gbit/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed using production-level 0.2-/spl mu/m GaAs MESFET technology.

Flip-flop cell having clock skew protection

Abstract: A flip-flop cell having a main data input, a main scan data input, a main data output and a main clock input. The flip-flop cell includes a multiplexer having first and second inputs and an output. The first input is coupled to the main data input of the flip-flop cell and the second input is coupled to the main scan data input of the flip-flop cell. A first latch has a data input, a data output and an inverting clock input. The data input of the first latch is coupled to the output of the multiplexer. A second latch has a data input, a data output and a non-inverting clock input. The data input of the second latch is coupled to the data output of the first latch. A third latch has a data input, a data output and an inverting clock input. The data input of the third latch is coupled to the data output of the second latch, and the data output of the third latch is coupled to the main data output of the flip-flop cell. The inverting clock input of the first latch, the non-inverting clock input of the second latch, and the inverting clock input of the third latch are all coupled to the main clock input of the flip-flop cell.

Flip-flop circuit, and shift register circuit, serial-parallel converter and parallel-serial converter using the same

Abstract: The power consumption of a flip-flop circuit is reduced and an output magnitude is increased to prevent a malfunction from occurring often. In order to reduce the power consumption, an emitter-coupled logic with series gating is used for the master latch of the flip-flop circuit. A series gating is not used but an ECL having transistors connected in parallel is used for the gates of a slave latch so as to increase the output magnitude.

Flip-flop circuit operating on low voltage

Abstract: Disclosed herein is a flip/flop circuit of a master-slave type including master side and slave side latch/hold circuits 1 and 2 each being of an ECL vertical 1-step construction, first and second bias circuits 3 and 4 for biasing current sources Tr's 21 to 24 of these latch/hold circuits 1 and 2 and a control circuit 5 for pull-down controlling these first and second bias circuits 3 and 4 by clock signals. The current sources Tr's 21 to 24 are thus selectively rendered conductive and non-conductive to perform a flip-flop operation on a low power source voltage such as 1V or less.

D flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To surely store data in a sleep state and to attain a high speed changeover from the sleep state into an active state with respect to the D flip-flop consisting of CMOS logic circuits. SOLUTION: Transistors(TRs) 26, 28, 30, 32 of which the threshold voltage absolute value and gate width are selected relatively larger and TRs 27, 29, 31, 33 whose threshold voltage absolute value is selected relatively higher and whose gate width is selected relatively smaller are provided to CMOS inverters 20, 23 consisting of TRs of which the threshold voltage absolute value is selected relatively smaller and in an active mode, the TRs 26, 28, 30, 32 are conductive and in the case of the sleep mode, the TRs 26, 28, 30, 32 are nonconductive. COPYRIGHT: (C)1997,JPO

Circuit for coupling an event indication signal across asynchronous time domains

Abstract: A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event indication signal is received from the foreign domain at a first input terminal; and a host clock signal is received at a second input terminal. Edge-triggered flip flop circuitry of the circuit has a clock input, a data input, and a data output. The clock input is coupled to the second input terminal and the data input is coupled to receive a latch output signal. The edge-triggered flip flop circuitry clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal, in response to a transition in the host clock signal. Delay circuitry is coupled to the first input terminal to receive the event indication signal. The delay circuitry provides a delayed event indication signal having a phase that is delayed from the event indication signal. Transparent latch circuitry latches the delayed event indication signal responsive to a latch control signal, and combination circuitry is coupled to receive the event indication signal and the result event indication signal, and provides a combination thereof as the latch control signal.

Master/slave d-type flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of a mater/slave D-type flip-flop circuit integrated into an LSI with a high speed operation or the like, and to prevent the operation frequency of the LSI or the like from being deteriorated. SOLUTION: In a master/slave D-type flip-flop circuit integrated in an LSI with a high speed operation or the like, a data comparator circuit 8 is provided at the input side of the clock circuit of the master/slave D-type flip-flop circuit, and a gate for interrupting a system clock inputted to the pertinent master/slave D-type flip-flop circuit when held data are fetched from a master latch circuit 5a and a slave latch circuit 6a, and they match is provided at a clock circuit 7.

D type flip-flop

Abstract: PROBLEM TO BE SOLVED: To shorten a hold time, speed up operation, and lower power consumption by connecting two stages of master-side latches, which function to hold only a low level, in series. SOLUTION: The master-side latches A and B both hold only the low level. Then the output node 12 of the master-side latch A is connected to the input node 14 of a slave-side latch C and also connected to the input node 13 of the master-side latch B. Consequently, a high level and the low level are both held at the output node 12' of the master-side latch B. Therefore, even if input data at an input terminal D varies from the high level to the low level after a clock signal CLK varies to the high level, the high-level signal held at the output node 12' never disappears and write to the slave-side latch C which is carried out through a transistor 6 as a 2nd data transmitting means is never interrupted right after the clock signal CLK goes up to the high level.

Latch circuit and flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To reduce an area and a power consumption by using the specific number of transistors(TRs) in cross couple connected so as to store data thereby configuring a latch circuit and a flip-flop with the fewer number of TRs than that of a conventional circuit. SOLUTION: When the level of data at an output data terminal Q or an inverting output data terminal QN is a high level, since a capacitive load is connected to the output data terminal Q or the inverting output data terminal QN by two transistors(TRs) MN11, MN12, the data of high level are stored so long as the speed of a clock signal is high. When a clock signal at a clock terminal CK descends from 'H' to 'L', input data are outputted as they are again. Since two TRs only are employed less than those of a conventional circuit, the area and the power consumption are reduced. Furthermore, since a transmission gate at the entrance of a latch circuit is configured by P channel TRs only, no inverting clock signal is required. Thus, the power consumed in the latch circuit is much reduced. COPYRIGHT: (C)1997,JPO

Master slave system flip-flop circuit

Abstract: PURPOSE: To shorten a signal propagation delay time by supplying data which is inputted to and held in a master-side closed loop circuit and its inverted data to a slave-side open loop circuit at the same timing. CONSTITUTION: The output terminal of an inverter 12 is connected to the input terminal of an inverter 14 through a two-way transfer gate 7 and the output terminal of an inverter 13 is connected to the input terminal of an inverter 15 through a two-way transfer gate 8 to supply the data which is inputted to and held in the master-side closed loop circuit and its inverted data to the slave-side open loop circuit through two-way transfer gates 7 and 8. Then the data are latched by a slave-side loop circuit and also outputted to a data output terminal 3 and an inverted data output terminal 4. The signal propagation delay time up to the data output and the signal propagation delay time up to the inverted data output are both as long as one two-way transfer gate stage, and the signal propagation delay time up to the data output is made shorter than that of a conventional FF circuit to make possible high-speed operation.

Logic circuit simulator

Abstract: PROBLEM TO BE SOLVED: To automatically collate an execution result between two CPUs and to make check work efficient by comparing the state of a storage element at the timing of the separation of instruction execution. SOLUTION: Circuit information 101 and a test pattern 102 are input data of a first simulation 105. Then, a result 107 is generated. Circuit information 103 and a test pattern 104 are input data of a second simulation 106. Then, a result 108 is generated. A comparison timing detection means 109 outputs 111 the state of the storage element of a flip flop from the result 107 at the time matched with a retrieval condition being the combination of specified signal values in the result 107. Then, the state of the storage element is similarly outputted 112 from the result 108. A comparison means 113 compares whether both results are the same or not. At that time, time does not have important meaning and only the order relation of the change of the signal becomes the object of comparison. COPYRIGHT: (C)1998,JPO

Flip-flop device

Abstract: PURPOSE:To attain a faster operation without almost increasing power consumption by providing a transistor (TR) for data read time varying, a bias terminal pair or an auxiliary differential pair or the like. CONSTITUTION:A FET J21 whose data read time is variable is connected in parallel with FETJ1 whose drains connect to a data read section among FETs forming clock input differential pairs with respect to a conventional FF circuit. While a FETJ21 is connected to a data latch differential pair, since two FETs J1, J21 are connected to a data read differential pair, the FETJ21 is closed and much more current is supplied to the data read section differential pair more than the data latch differential section and the read time of the FF circuit is increased more than a data latch time. Thus, the current fed to a FET of the data read section is increased for one clock period while keeping constant power consumption. Moreover, the data read time is equal to the data latch time by turning off the FETJ21 to make the operation at a low frequency stable.

D flip-flop

Abstract: PROBLEM TO BE SOLVED: To provide a D flip-flop in which data are sent/received at a high speed between integrated circuits (DFFs), a clock skew caused in this case is reduced, and a latch error caused by the skew is prevented. SOLUTION: The DFF 1 is provided with a clock delay circuit 2 in which data are outputted from a data output terminal Q with a clock received by a clock input terminal C and a clock via a transfer gate, a transfer gate equivalent to two buffers is outputted to a clock outptut terminal CO to generate a clock signal whose delay time matches a data delay time Td and the clock is outputted to the clock output terminal CO. Since data and a clock signal are delivered on wiring of the same path to an output connection destination DFF, the effect by the wiring is cancelled and then no problem is caused to high speed transmission of signals between integrated circuits (DFFs). COPYRIGHT: (C)1997,JPO

A 1860 kG CMOS gate array with GTL input flip-flop circuits

Abstract: A 1860 kG CMOS gate array with a high speed I/O circuit using 0.35 /spl mu/m CMOS process technology, has been developed. 300 MHz synchronous data transmission through a 30 cm line has been achieved with a flip-flop circuit which can directly receive and store a low voltage swing signal. This circuit technique reduces the latency time of data transmission between 2 LSIs by as much as 1.7 ns compared with conventional circuits.

Flip-flop controller

Abstract: A flip-flop controller including a clock controller for enabling or disabling a clock signal in response to a clock enabling signal and one or more flip-flops for selectively latching a function mode signal or scan test mode signal in response to a mode selection signal while being synchronous with the clock signal, is provided. As a result, a test vector is easily generated, fault coverage is increased to a desired degree using relatively few test vectors. Also, power consumption can be reduced by disabling the unnecessary portion of the clock signal applied to the flip-flop.

Experimental operation of an RS flip-flop composed of nonlatching Josephson gates

Abstract: We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson junctions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 6.5 ps/stage is obtained under Josephson critical current density of 10 kA/cm/sup 2/. We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlO/sub x//Nb junction technology and its operation is demonstrated experimentally.

Rts generation circuit

Abstract: PURPOSE: To suppress abnormal RTS generation regardless of the occurrence of racing in a flip flop circuit which latches RTS by outputting a gray code from a first counter in accordance with the latch signal of a second counter. CONSTITUTION: A 16 frequency division counter 20 as the first counter which outputs a numerical value at intervals of a clock period and a D flip flop circuit 14 as a first latch means which latches the output of this counter 20 in accordance with the latch signal of an N frequency division counter 12 are provided. A gray code/binary code conversion circuit 16 which converts the gray code to a binary code is provided in the output of the D flip flop circuit 14. When the counter output to be latched is the gray code, the number of bits of racing is one at most even if racing occurs, and either of adjacent codes is latched. Consequently, reproducing of an abnormal frequency on the reception side is prevented.