Showing papers on "Flip-flop published in 1999"

Miller and noise effects in a synchronizing flip-flop

Abstract: The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.

Sense amplifier-based flip-flop

Abstract: Timing elements, latches and flip-flops, are critical to performance of digital systems, due to tighter timing constraints and low power requirements. Short setup and hold times are essential, but often overlooked. Recently reported flip-flop structures achieved small delay between the latest point of data arrival and output transition. Typical representatives of these structures are sense amplifier-based flip-flop (SAFF), hybrid latch-flip-flop (HLFF) and semi-dynamic flipflop (SDFF). Hybrid flip-flops outperform reported sense amplifier-based designs, because the latter are limited by the output latch implementation. SAFF consists ofthe sense amplifier in the first stage and the RS latch in the second stage.

Current mode logic circuit, source follower circuit and flip flop circuit

Abstract: A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1 and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Low-power flip-flop circuit employing an asymmetric differential stage

Abstract: A flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the “output side” and the “reference side,” are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i.e., is placed in an opaque state), and retains its present state. Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion. In yet an additional embodiment, complex logic may be added to the differential stage of the flip-flop circuit.

Frequency divider, a phase lock oscillator and a flip-flop circuit using the frequency divider

Abstract: A frequency divider comprises first and second basic gates. Each basic gate includes first and second differential circuits, an adder unit for adding outputs from the first and second differential circuits and a buffer circuit to which an output from the adder unit is input. In the frequency divider, the adder units of the first and second basic gates receive negative feedback respectively from the adder units of the first and second basic gates and the second differential circuits through the buffer circuits of the first and second basic gates. An output from the adder unit of the first basic gate is connected to an input of the first differential circuit of the second basic gate, and an output from the adder unit of the second basic gate is fed back to an input of the first differential circuit of the first basic gate. The frequency divider further comprises a first current source for supplying a current in common to the first differential circuits of the first and second basic gates, a first current switching circuit inserted between the first current source and the first differential circuits of the first and second basic gates, and second and third current sources for respectively supplying currents to the second differential circuits of the first and second basic gates. A differential input signal is input to the first current switching circuit and a frequency-divided output signal is obtained from the buffer circuit of the second basic gate.

Limitations on HTS single flux quantum logic

Abstract: There is widespread interest in transferring Single Flux Quantum (SFQ) logic from niobium technology to a suitable HTS technology. The higher operating temperature results in increased noise and associated errors. We have developed numerical methods to study noise induced errors and how they depend on circuit parameters. A simple picture holds for all the circuits studied to date. The error probability shows an error function (integrated Gaussian) distribution. The width of the distribution is circuit dependent, but is 1 to 4 times the noise contribution of a single junction, and the noise free (deterministic) margin corresponds to the point where the error probability is 0.5. The distributions are frequently asymmetric, and minimum error rate does not occur for a design centered between the deterministic margins. A stochastic optimizer has been developed that allows us reoptimize circuits for conditions when noise induced margin narrowing is important. We have used this to study the influence of layout induced stray inductance on the feasibility of HTS circuits using the T flip-flop as an example. Stray inductance appears to be as important as junction reproducibility, and significant improvements are needed to allow high operating temperatures.

Low power double edge-triggered flip-flop using one latch

Abstract: A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit data are sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.

Scan flip-flop circuit

Abstract: A scan flip-flop circuit includes first and second master latches, a slave latch, and first, second, and third switches. The first master latch latches a data input signal and outputs it to the first output terminal in normal operation. The second master latch latches a scan input signal and outputs it to the second output terminal in a scan test. The slave latch latches an output from the first master latch that is input to a first input terminal, thereby outputting it to a third output terminal in normal operation, and latches an output from the second master latch that is input to a second input terminal, thereby outputting it to the third output terminal in a scan test. The first switch disconnects the first output terminal of the first master latch from the first input terminal of the slave latch in a scan test. The second switch disconnects the first output terminal of the second master latch from the second input terminal of the slave latch in normal operation. The third switch connects the second output terminal of the second master latch to the first input terminal via the second input terminal of the slave latch upon ON operation in a scan test, and disconnects the second output terminal of the second master latch from the first input terminal of the slave latch upon OFF operation in normal operation.

Flip-flop circuit

Abstract: A low power, high performance flip-flop includes a first branch having a number of transistors connected in series, and a second branch having a number of transistors connected in series. A clock signal and a data input signal are coupleable to the first and second branches of the circuit, the circuit generating a stable logic one or logic zero. The circuit has low power consumption and high performance speed.

Interlaced master-slave ECL D flip-flop

Abstract: A D flip-flop circuit operating in master-slave configuration which has low power consumption and is capable of high-speed operation, and a method for lowering power consumption in such a circuit is provided. The circuit embodiment includes two latches, each with a switching and memory section, and two interlaced current sources. In response to the active high clock signal the master latch memory section uses the current from the first current source while the slave latch switching section uses the current from the second current source, and vice versa. The switching section of each latch is biased with a higher current than the memory section, to provide the circuit with low power consumption. The output current provided to the switching section is preferably substantially twice the magnitude of the current provided to the memory section. The ratio of the currents of the current sources for the switching and memory section is preferably in the range of about 30% to 70%, depending on the clock frequency.

Digital phase-frequency detector

Abstract: In a digital phase-frequency detector with anti-backlash pulses, which prevent the mapping of very short correction pulses occurring on the basis of small phase differences by use of an AND logic circuit controlling the RESET of two flip flop circuits, a waste time is shortened by reducing a duration of the RESET pulse. The integrable phase-frequency detector according to the invention can be used in fast digital phase-locked control loops, for example for tuners, frequency synthesizers in the field of mobile radio.

Master slave flip flop as a dynamic latch

Abstract: A flip-flop circuit comprising a dynamic master coupled to a clock, the clock being characterized by an active stated of a limited duration, and a static latch coupled to the clock and coupled to the dynamic master. In an embodiment, the limited duration is less than the minimum time period in which the master can change from a first state to a second state.

An Optoelectronic Logic Gate Monolithically Integrating Resonant Tunneling Diodes and a Uni-Traveling-Carrier Photodiode

Abstract: InP-based InGaAs/AlAs/InAs resonant tunneling diodes (RTDs) and a uni-traveling-carrier photodiode (UTC-PD) are monolithically integrated to construct an optoelectronic logic gate. RTD structures are regrown by molecular beam epitaxy on the top of UTC-PD structures grown by metalorganic chemical vapor deposition. The characteristics of the regrown RTDs are almost the same as those of conventional RTDs directly grown on semi-insulating InP substrates. The UTC-PD provides a sufficient current drivability along with a high-speed operation demonstrated by the 3-dB bandwidth of 80 GHz, even at the low bias voltage corresponding to the peak voltage of the RTD. An optoelectronic logic gate using two RTDs and one UTC-PD was fabricated. This simple optoelectronic logic gate exhibited high-speed delayed flip-flop operation of 40 Gbit/s at a small power consumption of 7.75 mW. These results suggest that an optoelectronic logic gate using RTDs and a UTC-PD is suitable for the construction of ultrahigh-speed and low-power optoelectronic circuits.

Gated clock flip-flops

Abstract: A gated scan flop circuit and methods of making the gated scan flop circuit are provided. In one example, the scan flop circuit includes a sub-scan flop circuit that incorporates a multiplexer and a flip flop circuit, and a data terminal D that is connected to the sub-scan flop circuit. Also provided is a first logic gate that is configured to receive a scan input terminal SI and a clock gate terminal G. The first logic gate has a first logic gate output that is connected to the sub-scan flop circuit. A scan enable terminal SE is connected to the sub-scan flip circuit, and a latch circuit is configured to receive the clock gate terminal G, and track its input while the clock terminal CLK is inactive. A second logic gate having a second logic gate output is provided that is configured to receive as inputs the scan enable terminal SE and the latched clock gate terminal G. A third logic gate is configured to receive a clock terminal CLK and the second logic gate output. The third logic gate has a third logic gate output that is connected to the sub-scan flop circuit. The gated scan flop circuit has an output Q and a complementary output /Q. In this example, the first logic gate, the latch circuit, the second logic gate, the third logic gate, and the sub-scan flop circuit are internally integrated circuit components of the scan flop circuit.

Flip-flop circuit with clock signal controlling function and clock control circuit

Abstract: PROBLEM TO BE SOLVED: To suppress the power consumption of a flip-flop circuit. SOLUTION: The flip-flop circuit 10 is provided with a mismatch detecting circuit DDC and a clock controlling circuit CCC. The circuit DDC detects mismatch between a data input signal DIS and a data output signal DOS of the circuit 10. When the signal DIS and the signal DOS are mismatched, the circuit CCC supplies a short pulse for the circuit 10 as an internal clock signal ICLK by synchronizing with the rising of an external clock signal ECLK. Whereas, when the signal DIS and the signal DOS match with each other, the circuit CCC supplies a low-level signal for the circuit 10 as the signal ICLK. Thus, it is possible to avoid generating of an error in flip-flop operation while suppressing power consumption required for supplying a clock signal.

System and method for implementing a skew-tolerant true-single-phase-clocking flip-flop

Abstract: An exemplary skew-tolerant true-single-phase-clocking (TSPC) flip-flop is disclosed that reduces current spikes by allowing willful introduction of skew in the clock tree of a single-phase circuit design. More precisely, a split-clock TSPC flip-flop, which allows the flip-flop hold times to be met in the face of skewed clocks, which, in turn, reduces the maximum value of current spikes, can be substituted for a traditional TSPC flip-flop in a sequential logic circuit. The input of the split-clock TSPC flip-flop is latched according to a first clock signal, which was used in a preceding stage, while the output of the split-clock TSPC flip-flop is driven according to a second clock signal. The first and second clock signals can be skewed in time, but have the same frequency and substantially the same phase. Metal Oxide Semiconductor (MOS) device can also be included within the split-clock TSPC flip-flop to reduce power dissipation in cases of large clock skew.

D-type master-slave flip-flop

Abstract: The bistable circuit comprises a master unit (M) receiving an input variable (D) and producing first intermediate variables (M,NM). A transfer unit (T) contains two logic gates (3,4) with a clock signal connection (CK). This produces second intermediate variables (X,Y) as functions of the input variable and the clock signal, which are fed back to the master unit. A slave unit (E) produces at least one output variable (Q,NQ). One input of logic gate (3) is connected directly to receive the intermediate variable (M), and one input of logic gate (4) is connected via an inverter (5) to receive a complement (I) of the variable (M). The intermediate variables (X,Y) are mutually independent. In the preferred embodiment, each unit, master, transfer, and slave (M,T,E), contains two NAND gates. In the second embodiment the slave unit contains a NAND and a NOR gates, and two additional inverters. In the third embodiment the master unit contains a NAND and a NOR gates, and an additional inverter in one feedback loop. In the fourth embodiment the master unit is as in the third embodiment, and the slave unit as in the second embodiment. In the fifth embodiment the transfer unit contains an additional NOR gate connected to a control input (CN) via an inverter for set or reset. In the sixth embodiment the master and the slave units are with control inputs (CN). In the seventh embodiment the units are as in the preferred embodiment, but all with NOR gates. In the eighth embodiment the balanced circuit is connected for use as a divisor by two circuit, where the intermediate signals (X,Y) are in counter phase with frequency equal to half that of the clock signal.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To provide a flip-flop circuit which is not affected by delay in normal operation without being increased in circuit scale when a test is conducted in a through state SOLUTION: A signal which is in phase with a clock signal C and its inverted signal CB are supplied to the transfer gates (12, 13) of a slave latch A signal MC which is outputted by a control circuit 10 composed of a NAND circuit, receiving the clock signal C and a control signal T, and its inverted signal MCB are used as signals for controlling the transfer gates of a master latch so as to put the master circuit in a through state at the time of a test with the control signal

S-R flip-flop circuit

Abstract: An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.

Design of a fully-static differential low-power CMOS flip-flop

Abstract: A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson (see IEEE Jour. of Solid-State Circuits, vol. 32, no. 1, p. 62-9, 1997) in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure is shown to consume less power and occupy a smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures.

From a fuzzy flip-flop to a MVL flip-flop

Abstract: The paper presents a circuit description of a MVL flip-flop which is implemented in MOS technology. The circuit has its origins in a bipolar implementation of a fuzzy flip-flop. The proposed circuit not only simplifies the original bipolar design but it offers considerable potential for a VLSI implementation. Simulation of the circuit using HSpice indicates that it can also be interpreted as a multiple-valued logic flip-flop for any radix. This provides a basic building block for the increasing developments in multiple-valued VLSI circuit design.

Latch circuit provided with clock signal level conversion function, and flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To prevent leakage current from flowing through a flip-flop circuit. SOLUTION: This flip-flop circuit provided with a master latch circuit ML and a slave latch circuit SL is driven by voltage VDD1. A clock signal CK is amplituded between voltage VDD2 lower than the voltage VDD1 and ground voltage. A clock signal level conversion circuit CLC is arranged on a front stage for inputting the clock signal to the FF circuit. The circuit CLC boosts the voltage VDD2 of the clock signal CK to the voltage VDD and then inputs a high voltage clock signal CK to the FF circuit. Consequently the leakage current can be prevented from flowing through the flip-flop circuit.

Flip-flop circuit for scan path test and simulation method thereof

Abstract: PROBLEM TO BE SOLVED: To provide a flip-flop circuit for scan path test capable of suppressing operation current in the scan path test and reducing the time necessary for simulation using a scan path, and to provide a simulation method thereof. SOLUTION: In this flip-flop circuit for scan path test, a gate circuit 230 is provided in the following stage of a latch circuit comprising a master latch part 210 and a slave latch part 220. The gate circuit 230 blocks outputs, from the flip-flop circuit, of either of regular output data Q, Qb outputted to a circuit of a tested target and output data SIN for scanning outputted to a following flip-flop circuit according to an operation mode. Thereby, the unnecessary data output from the flip-flop circuit is adaptively blocked to suppress generation of an unnecessary event or unnecessary circuit operation. Accordingly, the operation current and the simulation time are reduced.

Experimental realization of a 3D integrated RSFQ T-flip-flop using stacktrons

Abstract: Superconducting circuits based upon Rapid Single Flux Quantum (RSFQ) Logic are an interesting approach for future digital electronics with clock frequencies in the range of 100 GHz. Our intention is to increase the integration density of such circuits. Therefore we have successfully fabricated and tested an RSFQ-circuit based on a new kind of stacked three terminal device, henceforth called a "stacktron". A stacktron consists of two vertically arranged all-niobium tunnel junctions, each separately shunted by a thin film resistor, and an access to the intermediate niobium layer. An RSFQ frequency divider (T-flip-flop) including two stacktrons has been tested up to 20 GHz. As a shunt resistor we used Pd/Au, so that /spl beta//sub c/<1 and the IV-curve is nonhysteretic. The junctions showed a current density of approximately 250 A/cm/sup 2/. The I/sub c/R/sub n/-product was 100 /spl mu/V. These first steps toward a three dimensional (3D) RSFQ architecture will be discussed in the framework of highly integrated and complex RSFQ-circuits.

Digital and analog measurements of HTS SFQ RS flip-flops and shift register circuits

Abstract: We fabricated reset-set (RS) flip-flops and shift registers by using YBCO bicrystal junctions and tested their operations by using a computer-controlled digital measurement set-up and an analog measurement set-up. The RS flip-flop circuits operated successfully at temperatures up to 71 K. The RS flip-flop circuit was observed over 600 computer-generated clock cycles with nearly no errors. The circuits were reset or set during each clock cycle. By using an analog measurement technique, we operated the RS flip-flop circuits at frequencies of up to 500 Hz. Since our probe was not designed for high speed operation, the test speed was limited to this frequency. Although we could not operate the shift register completely, we observed flux propagation in the shift register.

Latch circuit, flip-flop and combination circuit

Abstract: PROBLEM TO BE SOLVED: To reduce a circuit area and a test time in the case of conducting a scanning test by latching input data synchronously with a prescribed clock signal and selecting a latch operation or a through-buffer operation of a through- buffer. SOLUTION: With a control signal S set to 0, when a value of a latch enable signal G received by a NAND circuit 11 is 0, a value D1 of a data signal received by a D input 13C is outputted to a Q output 17. When the value of the latch enable signal G changes to 1, even when the value of the data signal received by a D input 13C changes to D2, an output from the Q output 17 is not immediately changed but keeps the value D1. In this case, the value D2 at the D input 13C is outputted to the Q output 17 when the latch enable signal G changes to 0. Furthermore, the control signal S is set to 1, even when the latch enable signal G is at '1', when the D input changes to a value D3, the value is outputted to the output Q.

C-axis microbridges for rapid single flux quantum logic

Abstract: The c-axis microbridge (CAM) junction technology has an inherently low inductance due to its groundplaned geometry which should be well suited to SFQ logic applications. However, the critical currents of the conventional (2 /spl mu/m diameter) CAM technology are too high. Experiments with optical lithography have shown that junctions of /spl sim/0.5 micron dimension are required. A new process using electron beam lithography has been developed. The junction statistics even at this early stage of development look promising. To confirm the validity of the rest of the design and fabrication technology a CAM based RS Flip-Flop has been fabricated which shows the correct traversal of the state graph at 45 K.

Latch circuit having voltage level conversion function and flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To reduce the number of required elements, to reduce power consumption and to accelerate an operation speed by providing a latch circuit with a voltage level conversion function. SOLUTION: When a clock signal CK is high, both transmission gates TG1 and TG2 become conductive. A slave latch circuit SL becomes a circuit which increases a voltage level of an intermediate output signal from a data output terminal Q1 in a master latch circuit ML and makes it pass through as it is when the signal CK is high. That is, since the voltage of the signal is VDD2 when the intermediate output signal from the terminal Q1 is high, the voltage VDD2 is converted into VDD1 that is higher voltage than it and an output data signal OD is outputted as a high signal. On the other hand, since the voltage of the signal is ground when the intermediate output signal of the terminal Q1 is low, the ground potential is just outputted as the signal OD.

Bipolar/CMOS current-source flip-flop for application in neuro-fuzzy systems

Abstract: A new current source flip-flop is presented which delivers an analogue current according to the state it stores. To enhance precision the output current is delivered while the main transistors are biased as CMOS compatible lateral bipolars. For reading and writing, these transistors are biased as regular MOS transistors. The resulting cell is extremely compact, allows low-voltage operation and is useful for neural and fuzzy based mixed mode processing systems.