Showing papers on "Flip-flop published in 2000"

Improved sense-amplifier-based flip-flop: design and measurements

Abstract: Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

High-performance energy-efficient D-flip-flop circuits

Abstract: This paper investigates performance, power, and energy efficiency of several CMOS master-slave D-flip-flops (DFF's). To improve performance and energy efficiency, a push-pull DFF and a push-pull isolation DFF are proposed. Among the five DFF's compared, the proposed push-pull isolation circuit is found to be the fastest with the best energy efficiency. Effects of using a double-pass-transistor logic (DPL) circuit and tri-state push-pull driver are also studied. Last, metastability characteristics of the five DFP's are also analyzed.

Hybrid latch Flip-Flop with Improved Power Efficiency

Abstract: An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase.

Low power flip-flop with clock gating on master and slave latches

Abstract: A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity.

Double-edge-triggered flip-flop providing two data transitions per clock cycle

Abstract: An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.

Flip-flop circuit

Abstract: The flip-flop circuit includes: a series (8) circuit which has a negative differential resistance element (1) and another negative differential resistance element (2) that has a control terminal capable of controlling a value of an element current; a transfer gate (9); a latch circuit (10) which has negative differential resistance elements (4), (5) connected in series; and an inverter circuit (11) which has an FET (6) as a drive element and a negative differential resistance element (7) as a load element. With this, such a flip-flop can be obtained that when a clock signal (CLK) is applied to a power supply terminal DD1 of the series circuit (8) and a control terminal of the transfer gate (9) and an input signal (IN) is supplied to the control terminal of the negative differential resistance element (2), an output is placed at a terminal.

High speed latch and flip-flop

Abstract: A latch and flip-flop are disclosed that have a reduced clock-to-q delay and/or a reduced setup time. This is preferably accomplished by providing both a data input signal and a complement data input signal to the latch or flip-flop. The data input signal and the complement data input signal are selectively connected to opposite sides of a pair of cross-coupled gates (409, 410) via a switch or the like. The switch is preferably controlled by an enable signal, such as a clock. With the switch elements enabled, the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal. Because the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal, the clock-to-q time may be reduced. In addition, because the data input signal and the complement data input signal drive opposite sides of the cross-coupled pair of gates, the state of the cross-coupled pair of gates can be more quickly set to a desired state. This helps reduce the clock-to-q time, as well as the setup time.

Modeling and optimized design of current mode MUX/XOR and D flip-flop

Abstract: This paper deals with current mode logic (CML) and, in particular, models and optimized design strategies for MUX, XOR, and D flip-flop are presented. Both simple and accurate models for propagation delay are proposed. The models represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need only a few SPICE simulations to properly evaluate model parameters. The simple models show errors which are always lower than 20%, while accurate models have typical errors of 2%. Design optimization is in terms of bias currents giving minimum propagation delay, and it has been demonstrated that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 and 20 GHz, respectively.

Non-volatile flip-flop circuit

Abstract: A combination non-volatile latch circuit has a volatile latch circuit having a bit signal and an inverse bit signal. A first and a second non-volatile cell of the split gate floating gate type having a first terminal, a second terminal and a control gate is supplied. A first switch supplies the bit signal to the first terminal of the first cell and the inverse bit signal to the first terminal of the second cell. A second switch supplies the bit signal to the first terminal of the second cell and the inverse bit signal to the first terminal of the first cell. A first voltage can be supplied to the second terminal of the first and second cells and a second voltage supplies a voltage to the control gate of the first and second cells. In this manner, the latch can be operated independently of the non-volatile memory cells, the status of the latch can be restored by the status of the non-volatile memory cells, and the contents of the latch can be stored in the non-volatile memory cells.

Dynamic flip-flop with improved power

Abstract: An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. This is accomplished by equalizing the t/sub pLH/ and t/sub pHL/ of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.

Pulsed circuit topology including a pulsed, domino flip-flop

Abstract: A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.

CMOS sense amplifier-based flip-flop with two N-C2MOS output latches

Abstract: By replacing the NAND SR latch at the output stage of a conventional sense amplifier-based flip-flop (SAFF) by two N-C2MOS latches, the operating speed of the flip-flop is enhanced by 63% and the power-delay-product is reduced by 28%.

Clock enable control circuit for flip flops

Abstract: A clock enable control circuit for controlling flip flops on a programmable logic device. The clock enable control circuit either passes an original data signal to the input terminal of a flip flop, or feeds back an output signal from the output terminal to the input terminal of the flip flop in response to a clock enable control signal. The clock enable control signal is selected from one of a set control signal and a reset control signal that are otherwise provided on the programmable logic device to selectively control set and reset functions of the flip flop. In one embodiment, the set and reset control signals are generated as product-term signals that are programmably routed by a product-term allocator circuit to a macrocell including the flip flop and the clock enable control circuit.

High performance, low power, scannable flip-flop

Abstract: A dual-edge pulse-triggered flip-flop comprising a gated data latch and a gated scan latch coupled in series with the data latch. In normal operation, the data latch captures a data input D in response to clock pulses ckp generated on each edge of a system clock ck. During an input scan operation, a selected stimulation bit presented on a scan input SI is transferred first into the scan latch in response to a scan input clock ak, and then into the data latch in response to a scan output clock bk. This stimulation bit is simultaneously presented on a scan output SO. During an output scan operation, a data bit Q presented on the scan input SI is transferred first into the scan latch in response to the scan input clock ak, and then into the data latch in response to the scan output clock bk. This data bit is simultaneously presented on the scan output SO. A scan chain can be formed by coupling the scan input SI of a first flip-flop to the scan output SO of a second, upstream flip-flop, and the scan output SO of the first flip-flop to the scan input SI of a third, downstream flip-flop.

High-speed, compact, edge-triggered, flip-flop circuit

Abstract: A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section. In the first embodiment, the output circuit section includes a plurality of FETs which perform second stage of latching such that the output of this section reflects the logic of the chosen inputs only at the occurrence of either a low-to-high transition or a high-to-low transition on the clock signal, but not both, depending on the chosen configuration of the flip-flop circuit. In a second embodiment, a D flip-flop circuit includes a latch circuit section which includes at least one NDR diode connected to the data output of the input circuit section and an output circuit section which also includes at least one NDR diode connected to the output of the output circuit section. In the second embodiment, the flip-flop circuit may use: 1) bistable NDR logic; 2) cascaded NDR latches; or 3) pseudo-bistable NDR logic with a true, single-phase clock.

Dynamic flip-flop with improved power

Abstract: An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the tpLHand tpHLof the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.

Flip flop circuit

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption by reducing the frequencies of a clock signal in a circuit in which timing adjustment is relatively simple while suppressing the increase of a circuit area by reducing the number of elements. SOLUTION: A latch circuit 1 fetches an input signal FD when a clock signal CLK is in an H state. A latch circuit 2 fetches the input signal FD when the clock signal CLK is in an L state. A multiplexer 3 selects an output signal Q of the latch circuit 1 when the clock signal CLK is in the L state, or selects the output signal Q of the latch circuit 2 when the clock signal CLK is in the H state, and outputs it. Thus, it is possible to fetch the input signal in both the rising and falling states of the clock signal. Consequently, the frequencies of the clock signal can be reduced into half, and power consumption can be reduced by reducing the frequencies of the clock signal.

High phase margin low power flip-flop

Abstract: An improved flip-flop circuit exhibits a higher phase margin than conventional flip-flop circuits without a substantial increase in operating power. The flip-flop circuit includes a master latch circuit operatively coupled to a slave latch circuit. The flip-flop circuit uses any number of techniques to delay the hold-to-sample transition of the slave latch circuit relative to the sample-to-hold transition of the master latch circuit. The delay enables the flip-flop circuit to better tolerate clock/data timing alignment issues. In a first embodiment, the slave clock signal is delayed relative to the master clock signal. In a second embodiment, the master clock signal buffer is unbalanced such that its duty cycle is skewed to produce unequal sample and hold periods. In a third embodiment, the master latch circuit is unbalanced to create an unequal delay associated with the sampling and holding periods.

D flip-flop structure with flush path for high-speed boundary scan applications

Abstract: A boundary scan cell includes a shift latch, an update latch and a flushable latch that each have at least a respective data input and at least a respective data output. The data output of the shift latch is coupled to the data input of the update latch. The boundary scan cell further includes control circuitry that controls operation of the flushable latch circuit. The control circuitry selects, as input data for the flushable latch, one of a functional logic signal and a boundary scan signal in response to a mode signal. If the mode signal indicates a test mode, the control circuitry selects the boundary scan signal as the input data and causes the flushable latch to flush through the input data to the data output of the flushable latch independent of a system clock signal. The boundary scan cell can be implemented as either an input or output cell and preferably is compliant with IEEE Std 1149.1.

Dual rail dynamic flip-flop with single evaluation path

Abstract: A dynamic flip-flop circuit that operates in a pre-charge phase and an evaluation phase allows for implementation of multiple-input logic functions without sacrificing performance by using a single evaluation path to generate its output signals. In one embodiment, the dynamic flip-flop circuit includes input logic that receives a clock signal and one or more data input signals. The clock signal defines the pre-charge phase and the evaluation phase of the flip-flop circuit. The input logic has an output terminal connected to a first output buffer circuit, which in turn drives the flip-flop circuit's Q output signal. The output terminal of the input logic is combined with the clock signal in a logic gate having an output terminal connected to a second output buffer circuit, which in turn drives the flip-flop circuit's complementary output signal {overscore (Q)}. During the pre-charge phase, the input logic forces the Q output signal to a first logic state via the first output buffer, and the logic gate forces the {overscore (Q)} output signal to logic low via the second output buffer. During the evaluation phase, the input logic generates a logic signal in response to a predetermined logic function of its one or more input signals. The logic signal(s), in turn, drives the Q output signal via the first output buffer, and drives the {overscore (Q)} output signal to a complementary logic state via the logic gate and second output buffer.

Pipelined compressor circuit

Abstract: A pipelined four-to-two compressor includes sequential elements with embedded logic. One sequential element is a flip flop with complementary outputs that includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. Keeper nodes can also be dynamic flip flop outputs that pre-charge each clock cycle. Another flip flop with embedded logic receives the dynamic output, applies further logic, and provides a static output.

Method and apparatus for integrated flip-flop to support two test modes

Abstract: A circuit, an integrated flip flop, to receive an input in response to a clock signal. The integrated flip flop has a first and second slave latch and a master latch. The first slave latch receives an output from the master latch in response to the clock signal and a control signal for a first test mode of operation. The second slave latch receives an output from the master latch in response to the clock signal in one of a second test mode of operation or a normal functional mode of operation.

Reduced-transistor, double-edged-triggered, static flip flop

Abstract: A static, double-edge-triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loops share a forward path having a data-inverting circuit. In addition, each loop has a feedback path which contains only one element in the form of a switch. However, no data-inverting circuit is included in either of the feedback paths. Advantageously, all the elements of the flip-flop may be constructed using MOSFET transistors implemented according to any one of a variety of semiconductor technologies. In more than one particularly advantageous embodiments, the flip-flop is constructed using a total of twelve transistors. Through this simplified two-loop design, operational efficiency is improved, low metastability is achieved and costs of manufacture are lowered, all while maintaining low power requirements.

Method and apparatus for a scannable hybrid flip flop

Abstract: A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.

Improving path delay testability of sequential circuits

Abstract: We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible.

Flip-flop having gated inverter feedback structure with embedded preset/clear logic

Abstract: A flip-flop having one or more stages (e.g., a master stage and a slave stage in a master-slave flip-flop, or a single stage as in a latch), at least one stage having a driver coupled at its input and output to a feedback path with a gated inverter having embedded preset and/or clear logic. By embedding the preset/clear logic in the feedback path, the driver can be implemented using a simple inverter. Moreover, the preset and/or clear functionality can be added without adversely affecting either the setup time or the clock-to-Q propagation time of the flip-flop.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To operate a flip-flop circuit at high speed which is the important component of a semiconductor integrated circuit and to reduce the space required. SOLUTION: A first latch circuit 1 for fetching data is of dynamic type, a second latch circuit 2 for storing, holding and outputting the data is of a static type. Both circuits 1 and 2 are connected serially and connected through a buffer circuit 14 to an output terminal Q. A switch control circuit 15 receiving a clock CK complementarily operates a first switch circuit 11 and a second switch circuit 12. A capacitor Cm parasitic to a node A holds a signal D only in the OFF period of a switch 11, shifts it to a second storage circuit 13 at the fall of the CK and statically holds it. The second storage circuit 13 is composed of an inverter and a clocked inverter for instance and constitutes a positive feedback loop by control from the switch control circuit 15.

Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop

Abstract: A novel T-gate consisting of multi-junction surface tunnel transistors (MJ-STTs) and hetero-junction FETs (HJFETs) were proposed and its operation was successfully confirmed by both simulation and experiment. The number of the devices required for their-gate can be drastically reduced due to a high functionality of the MJ-STT. Only three MJ-STTs and three HJFETs were required to fabricate the three-valued T-gate, whose number is less than one half of that of the conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic function. Furthermore, a multiple-valued data flip-flop (D-FF) circuit could be realized by only one T-gate.