Showing papers on "Flip-flop published in 2002"

A low-swing clock double-edge triggered flip-flop

Abstract: A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-V/sub t/ transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network.

High-speed fully balanced differential flip-flop with reset

Abstract: A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a differential reset circuit. The clock circuit having complementary clock inputs to alternately set and store data in the data set and data store circuits. The differential reset circuit ties to the differential output and is operative in response to a reset signal to force the differential output to a predetermined logic level. The differential reset circuit includes matched complementary reset drivers to exhibit like capacitances. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell.

High-speed differential sampling flip-flop

Abstract: A high-speed differential sampling flip-flop includes a differential data input, a differential offset control input, a sampling clock input, an output, a sampling latch, and an RS latch. The sampling latch includes a sampling latch reset circuit, a current steering circuit, first and second switches, and a regenerative latch. The sampling latch reset circuit is coupled to a first power supply and the current steering circuit. The current steering circuit has first and second control terminals which are coupled to the differential data input. The first switch is coupled between the current steering circuit and a second power supply. The regenerative latch is coupled to the current steering circuit, the second switch, and a third power supply. The sampling latch also includes first and second offset control current sources coupled to the current steering circuit and the second power supply, and having first and second control terminals coupled to the differential offset control input. The RS latch includes two cross-coupled nand gates and is coupled to the sampling latch and the output. On a transition of the sampling clock input from logic low to logic high, the differential data input is sampled, amplified to a low or high logic level, and transferred to the output. The differential offset control input is used to control the input offset of the sampling flip-flop.

Semiconductor integrated circuit including conditional clocking flip-flop circuit

Abstract: A semiconductor integrated circuit including: a first latch to pass or store a signal in accordance with a logic value of a first internal clock signal; a second latch connected in series to the first latch, to pass or store a signal in accordance with a logic value of a second internal clock signal, with inverted operational characteristics in regard to the first latch; comparators to compare signal logic values at signal-input and -output nodes of the first latch; and the second latch; a first clock controller to generate a signal having a specific logic value in dependence on whether nodes of the first latch have the same or different signal logic values, as the first internal clock signal, based on the output of the first comparator; and a second clock controller to generate a signal having a specific logic value in dependence on whether nodes of the second latch have different signal logic values, as the second internal clock signal, based on the output of the second comparator.

Power up initialization circuit responding to an input signal

Abstract: A power up pulse generator circuit generates a pulse of predetermined duration in spite of a slow rate of change of applied power supply voltage. The circuit has application to integrated logic circuits that begin operation from an initial condition after the application of the power supply voltage and an input signal. In one embodiment, a dynamic random access memory (DRAM) of the present invention begins operation after receiving an address strobe signal. The address strobe signal is coupled to the power up pulse generator circuit to assure that the power up pulse is of sufficient duration to reset internal registers and so establish the initial condition. The power up pulse generator circuit of such an embodiment includes a selectively enabled input buffer, a selectively enabled one shot, and a flip flop designed to assume a predetermined state on application of the power supply voltage.

Circuit for preserving data in a flip-flop and a method of use

Abstract: A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

Method for distributing clock signals to flip-flop circuits

Abstract: A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a maximum delay constraint time for a clock in an input path to a flip-flop circuit, obtaining a timing slack of a second minimum delay time with respect to a minimum delay constraint time and a timing slack of a second maximum delay time with respect to a maximum delay constraint time for a clock in an output path from all the flip-flop circuits which receive the clocks from a clock terminal directly and obtaining a delay value which maximizes a minimum value of each of the first and second minimum delay time and maximum delay time of timing slacks.

A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors

Abstract: A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated Due to the combination of the MJSTTs latching function and the MOSFETs switching function, the number of devices required for the D-FF circuit was greatly reduced to three from the thirty required for the FET-only circuit

Flip flop circuit

Abstract: A dual rail flip flop with complementary outputs includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip flop operates in a pre-charge state and an evaluate state. During the pre-charge state when a clock signal is low, the flip flop pre-charges internal keeper nodes to a high value. When the clock signal transitions high, the flip flop enters an evaluation state and one of the internal keeper nodes evaluates to a low value. The sense stage senses which of the internal keeper nodes is evaluating to zero, and drives it to zero faster. The slave stages reflect the state of the internal keeper nodes during the evaluate state, and maintain their states during the pre-charge state.

Gated scan output flip-flop

Abstract: A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer is gated by a scan enable input so that the scan output is quiescent when the storage circuit is not in scan mode. The selectively enabled scan output buffer is embodied with only four transistors.

Circuit for asynchronous reset in current mode logic circuits

Abstract: A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.

Differential CMOS edge-triggered flip-flop with clock-gating

Abstract: A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when the switching activity of the input signal is <0.65. Power reduction can be as high as 86% when the input is idle.

Multi-valued flip-flop with neuron-CMOS NMIN circuits

Abstract: In this paper, the implementation and verification of the fundamental flip-flops for the voltage-mode multi-valued logic circuits on a conventional CMOS VLSI chip are presented. Using the quantized NMIN circuits and the analog NMIN circuits, two types of the multi-valued R-S flip-flop are designed like a wide-use R-S flip-flop with NAND circuits and are applied to the D flip-flop for multi-valued memory. In verification through HSPICE simulation, the proposed flip-flops perform with good results such as high noise margins and low power consumption.

Radiation tolerant flip-flop

Abstract: A flip-flop circuit comprising: a master latch circuit; a slave latch circuit coupled to the master latch circuit; and a correction circuit for increasing an amount of charge that can be absorbed by the master latch circuit in response to a soft-error event when the slave latch circuit is in a transparent phase and when both the master and slave latch circuits are storing the same data.

Flip-flop circuit with reduced power consumption

Abstract: A low power flip-flop is disclosed The number of transistors which are coupled to the clock signal is reduced by more than half when compared with known flip-flop designs The flip-flop comprises a pair of clocked transistors forming a pass gate and a plurality of inverters coupled thereto By reducing the number of clock signal connections needed for reliable operation, the present invention reduces the power consumed by the flip-flop when operating at typical levels of activity by up to 70%

Method and system for reducing hazards in a flip-flop

Abstract: The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.

Method and system for disabling a scanout line of a register flip-flop

Abstract: A method and apparatus for disabling the scan output of flip-flops contained within an integrated circuit. Registers within the integrated circuit form a serial shift register chain when in the test mode of operation. The registers contain therein flip-flops, each of the flip-flops having at least one data input, a scan test input, a data output, and a scan output. The flip-flop is capable of storing either the signal appearing on the at least one data input or the signal appearing on the scan test input, based on the mode of operation of the flip-flop. The flip-flop includes a circuit coupled between the data output and the scan output for selectively disabling the scan output from following the value of the data output. Consequently, the scan output is enabled to output the logic value stored in the flip-flop when the flip-flop is in the test mode of operation and is disabled from outputting the logic value stored in the flip-flop when the flip-flop is in the normal mode of operation. When the scan output is disabled from following the data output, the scan output is driven to a predetermined logic value.

Scan flip-flop and semiconductor integrated circuit device

Abstract: A scan flip-flop ( 100 A) that may operate as a positive flip-flop or a negative flip-flop in a normal operating mode has been disclosed. Scan flip-flop ( 100 A) may include a master latching circuit ( 11 ), a slave latching circuit ( 12 ), and a clock circuit ( 13 A). Clock circuit ( 13 A) may receive a signal (XA), a control signal (control), and a mode signal (SCN). Signal (XA) may select between a positive flip-flop operation and a negative flip-flop operation when in a normal operating mode. Mode signal (SCN) may select between a normal operating mode and a scan test mode. Control signal (control) may disable signal (XA) so that scan flip-flop ( 100 A) may operate in a known mode, such as a positive flip-flop, regardless as to the value of signal (XA). Scan flip-flop ( 100 A) may reduce logic gates in clock lines which may be required in a conventional approach.

2-level series-gated current mode logic with inductive components for high-speed circuits

Abstract: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

Technique for improving propagation delay of low voltage to high voltage level shifters

Abstract: The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors 24 and 26 and pull-down transistors 20 and 22. The falling-edge 1-shot circuits 34 and 36 output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop 38. The flip flop 38 provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.

A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)

Abstract: A new reduced clock-swing flip-flop, named NAND-type Keeper Flip-Flop (NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features a simple configuration, which does not have additional clock drivers or does not have additional nand/or p-wells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25 /spl mu/m CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flip-flop.

Silicon-on-insulator dynamic d-type flip-flop (DFF) circuits

Abstract: A novel dynamic DFF method and apparatus using CMOS is disclosed. The present invention does not use ratioed logic transistors in implementing a first stage of the DFF design. Thus, PMOS and NMOS transistors, used in the first stage of the DFF circuit, do not have severely disproportionate P-to-N transistor size ratios. These transistors therefore can have a transistor size ratio that increases the circuit's operating speeds.

Implementation of multiple flip flops as a standard cell using novel clock generation scheme

Abstract: Scan chain routing efficiency is improved in an integrated circuit (IC) such as an application specific integrated circuit (ASIC) by defining flip flop groupings prior to place and route. A flip flop grouping specifies the arrangement of multiple flip flops and the scan chain routing through those flip flops. The predetermined flip flop arrangement of the flip flop grouping then prevents undesirable flip flop placements during place and route. The flip flop grouping therefore minimizes the layout impacts of scan insertion while simplifying the place and route process. Different flip flop groupings can be used in a single IC design, and flip flop groupings can be combined with individual flip flops in the IC layout. A flip flop grouping can include control logic for the flip flops. Clock gating logic can be offloaded from the flip flops into the control logic to further improve layout efficiency.

A MOS approach to CMOS DET flip-flop design

Abstract: A novel approach to double-edge-triggered (DET) flip-flop design is presented along with a new static flip-flop and a new dynamic flipflop. The approach builds CMOS circuits using pass transistors and MOS-style clocked inverters and addresses issues of threshold voltage drop (V/sub T/ drop) and circuit complexity. Among DET designs, the number of switched and total transistors used by our flip-flops is less than or equal to any in related work. Our circuits beat all others in speed (maximum frequency response) by significant margins at medium to high supply voltages. The speed outperformance range for our static flip-flop is 1.5 to 5 V and for our dynamic flip-flop is <2.5 to 5 V.

Power reduction in scannable D-flip-flop with synchronous preset or clear

Abstract: In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

Design of high-speed master-slave D-type flip-flop in InP DHBT technology

Abstract: In this paper, we present some design problems of high-speed master-slave D-type flip-flop (MS D-FF). Essential to the long-haul optical-fiber communication systems, this circuit is critical since it operates at the highest clock frequency for a given bit rate. We discuss specific aspects of electrical design of such a circuit and underline some important points for the layout of gigabit circuits. In particular, we tackle the problem of ringing, which can appear in emitter-follower structures using the fast transistors necessary for high-speed operation. We have pointed out also some difficulties of circuit layout, particularly certain connections that can cause serious ill functioning. The MS D-FF was fabricated in our self-aligned InP double heterojunction-bipolar-transistor technology. On-wafer characterizations at 40 Gb/s show 75% horizontal and 68% vertical eye opening.

2-level series-gated CML-based circuit with inductive components for optical communication

Abstract: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

Phase locked loop clock divider utilizing a high speed programmable linear feedback shift register with a two stage pipeline feedback path

Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of “pre-load” flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.

Clocked-scan flip-flop for multi-threshold voltage CMOS circuit

Abstract: A clocked-scan flip-flop for multi-threshold CMOS (MTCMOS) is provided. The clocked-scan flip-flop includes a first switching unit which switches normal data that are input from the outside and outputs the data; a second switching unit which switches scan data that are input from the outside and outputs the data; a latch unit which latches the data input from the first switching unit or the second switching unit; and a clock input unit which controls the switching operations of the first and second switching units according to the result of a predetermined operation on a clock signal and a scan clock signal that are input from the outside. The clocked-scan flip-flop has the characteristics of a complementary pass-transistor (CP) flip-flop, that is, low power consumption and high performance. Also, the clocked-scan flip-flop provides a full-scale scan function for test purposes.

CMOS sequential logic configuration for an edge triggered flip-flop

Abstract: A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.