Showing papers on "Flip-flop published in 2003"

Molecular-junction-nanowire-crossbar-based inverter, latch, and flip-flop circuits, and more complex circuits composed, in part, from molecular-junction-nanowire-crossbar-based inverter, latch, and flip-flop circuits

Abstract: Methods for implementing familiar electronic circuits at nanoscale sizes using molecular-junction-nanowire crossbars, and nanoscale electronic circuits produced by the methods. In one embodiment of the present invention, a 3-state inverter is implemented. In a second embodiment of the present invention, two 3-state inverter circuits are combined to produce a transparent latch. The 3-state inverter circuit and transparent-latch circuit can then be used as a basis for constructing additional circuitry, including master/slave flip-flops, a transparent latch with asynchronous preset, a transparent latch with asynchronous clear, and a master/slave flip-flop with asynchronous preset. 3-state inverters can thus be used to compose latches and flip-flops, and latches and flip-flops can be used, along with additional Boolean circuitry, to compose a wide variety of useful, state-maintaining circuits, all implementable within molecular-junction-nanowire crossbars by selectively configuring junctions within the molecular-junction-nanowire crossbars.

Rapid single-flux quantum logic using π-shifters

Abstract: We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.

A low complexity and a low latency bit parallel systolic multiplier over GF(2/sup m/) using an optimal normal basis of type II

Abstract: Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2/sup m/), which has a low hardware complexity and a low latency We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches (flip-flops) On the other hand, most of other multipliers of the same type have latency 3m and the basic cell of each multiplier needs 7 latches Comparing the gates areas in each basic cell, we find that the hardware complexity of our multiplier is 25 percent reduced from the multipliers with 7 latches

A 225 MHz resonant clocked ASIC chip

Abstract: We have recently designed, fabricated, and successfully tested an experimental chip that validates a novel method for reducing clock dissipation through energy recovery. Our approach includes a single-phase sinusoidal clock signal, an L-C resonant sinusoidal clock generator, and an energy recovering flip-flop. Our chip comprises a dual-mode ASIC with two independent clock systems, one conventional and one energy recovering, and was fabricated in a 0.25 /spl mu/m bulk CMOS process. The ASIC computes a pipelined discrete wavelet transform with self-test and contains over 3500 gates. We have verified correct functionality and obtained power measurements in both modes of operation for frequencies up to 225 MHz. In the energy recovering mode, our power measurements account for all of the dissipation factors, including the operation of the integrated resonant clock generator, and show a net energy savings over the conventional mode of operation. For example, at 115 MHz, measured dissipation is between 60% and 75% of the conventional mode, depending on primary input activity. To our knowledge, this is the first ever published account of a direct experimentally-measured comparison between a complete energy recovering ASIC chip and its conventional implementation correctly operating in silicon at frequencies exceeding 100 MHz.

MTCMOS flip-flop circuit capable of retaining data in sleep mode

Abstract: The present invention relates to a flip-flop circuit employing an MTCMOS technology comprising a master latch unit and a slave latch unit, for latching input data and outputting the data under the control of an internal clock signal, wherein an output of the flip-flop circuit retains a state just before the admission to sleep mode when the state of the system is converted from sleep mode to active by means of making a data state of an input terminal of a master latch into the same state as an inversed data state of an input terminal of a slave latch circuit in sleep mode and storing it. The flip-flop circuit employing the MTCMOS technology in accordance with the present invention is capable of retaining a state just before the sleep mode when the state of the system is converted from sleep mode to active mode by using the sleep mode control signal by means of adding the feedback circuit to the conventional flip-flop circuit. In addition, while the flip-flop circuit employing the MTCMOS technology in accordance with the present invention has an operation speed slightly slower than that of the prior art flip-flop circuit employing the low-Vth transistor or the high-Vth transistor, a leakage current of the present invention is significantly smaller than that of the conventional art.

Optimization of scannable latches for low energy

Abstract: This paper covers a range of issues in the design of latches and flip-flops for low-power applications. First it revisits, extends, and improves the energy-performance optimization methodology, attempting to make it more formal and comprehensive. The data-switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of an energy-efficient family of configurations is introduced to make the comparison of different latch styles in the energy-performance space more fair. A recently proposed methodology for balancing hardware intensity in processor pipelines is applied to latch design to facilitate the selection of the objective function for tuning transistor sizes. The power dissipation of the clock distribution is taken into account, supported by simulations of extracted netlists for multibit datapath registers. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power level-sensitive scan mechanism is proposed, and results of a comparative study of scannable latches are shown. The applicability of the proposed scan mechanism to a wide variety of latches is demonstrated.

Master slave flip-flop circuit functioning as edge trigger flip-flop

Abstract: In a master latch circuit, input data signal is received in a data through state and is held in a data holding state as output data signal. In a slave latch circuit, the output data signal is received in a data through state and is held and output in a data holding state. In a circuit setting control unit, in response to a clock signal, the disconnection of a first line from a power source and the connection of a second line to a ground terminal in an NMOS transistor are performed to set the master latch circuit and the slave latch circuit to the data through state and the data holding state respectively, and the connection of the first line and the disconnection of the second line are performed to change the states of the latch circuits.

Methodology for verifying multi-cycle and clock-domain-crossing logic using random flip-flop delays

Abstract: A design tool inserts randomized delays into synchronizers for signals crossing from one clock domain to another. Rather than having a wide range of random delays to select from, each synchronizer's randomized delay is selected from only two possibilities. An added delay of either zero or one clock period of the new domain's clock is added as the randomized delay. The randomized delay causes the re-synchronized domain-crossing signal to become available either in the expected cycle or in the cycle following the expected cycle. Logic hazards caused by the domain-crossing signal can be detected and the possible results simulated. The synchronizer can be a series of two flip-flops, with the random delay added to the first flip-flop. Randomized delays of either one or none added periods of the clock can also be added to multi-cycle signals within one clock domain that have two or more clock cycles to propagate.

A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application

Abstract: In this paper, a low voltage dual-pulse-clock double edge triggered D-flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistors count is reduced to improve speed and power dissipation in flip-flop. The number of transistors is reduced by 40% to 70% compared to other double edge triggered flip-flops. Based on 0.35um single-poly quad-metal CMOS technology, the HSPICE simulation results show that the operating speed of the DPDET flip-flop is 2.7 GHz at a 3.3V supply voltage. The operating speed of the DPDET flip-flop is increased about 41% and 49% in compared with others for 3.3V and 2.5V supply voltage, respectively. The power dissipation is reduced about 36% and 29% in compared with others for 3.3V and 2.5V supply voltage, respectively. Moreover, the DPDET flip-flop can be used in a 0.9V supply voltage with 224 MHz operating speed. Therefore the proposed DPDET flip-flop is suitable for low supply voltage and high speed CMOS applications.

Data-enabled static flip-flop circuit with no extra forward-path delay penalty

Abstract: A logic circuit includes a data-enable controller for outputting a data value. When implemented as a master-slave flip-flop, a data enable signal controls the activation of a master stage of the flip-flop in conjunction with the transitioning edge of an input clock signal. The data enable signal also controls the feedback of a logical value stored in the slave stage to a storage node of the master stage. Operation of the slave stage may be controlled by the input clock signal only. Through this structural configuration, the flip-flop or latch outputs logical values without requiring any additional forward-path delay elements. As a result, these devices are faster and more efficient than conventional circuits.

Device for programmable frequency divider

Abstract: The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.

Scan flip-flop circuit, scan flip-flop circuit array, and integrated circuit device

Abstract: A scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector section, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array are provided. In a scan flip-flop circuit, an output terminal is provided in addition to an output terminal. One of the output terminals is used for a logic circuit and the other output terminal is used for a scan flip-flop circuit of the next stage. At the output terminal for the scan flip-flop circuit 1 of the next stage, an output is fixed in a normal operation, thereby achieving higher operation speed in the normal operation and lower power consumption. A selector section can employ a relatively simple OR-AND-INVERTER structure.

Low power flip-flop circuit

Abstract: A flip-flop circuit includes a latch that holds an input signal responsive to an internal clock signal, a comparing circuit that compares the input signal with a latch output to provide a comparison signal, and an internal clock generator that receives an external clock signal and generates an internal clock signal responsive to the comparison signal. The internal clock generating circuit performs a NAND operation on the external clock signal and a delayed inverted version of the external clock signal, to generate the internal clock signal having pulse width smaller than the external clock signal and having rising and falling edges synchronized with the external clock signal. Power consumption is low because the clock buffer and the internal clock generating circuit do not perform switching operations when there is little or no variation in the input signal of the flip-flop.

Low power flip flop

Abstract: A low power, high speed D type flip flop is disclosed. The D type flip flop uses four inverters and four transmission gates to store and output the data states. The flip flop comprises two memory elements wherein each memory element is made up of a transmission gate and two inverters. Each of the four inverters contained in the flip flop is referred to as a bypass current limiting inverter. Each of the four inverters contains biasing circuitry to limit current flow and thereby save power. Additionally, each inverter has switching circuitry that enables the current limiting features to be automatically and advantageously bypassed thereby allowing for large currents and fast response times whilst simultaneously retaining the low power performance.

Edge accelerated sense amplifier flip-flop with high fanout drive capability

Abstract: Flip-flop devices provide fast clock-to-Q timing that exploits the pulsed nature of outputs generated by a clocked sense amplifier. These flip-flop devices include an output stage, which has a PMOS pull-up transistor and an NMOS pull-down transistor therein, and a clocked sense amplifier at an input stage. The clocked sense amplifier is configured to generate first and second data output signals (/SET and /RESET). These data output signals are provided to a signal edge acceleration stage. This signal edge acceleration stage is configured to generate the pull-up and pull-down control pulses in response to the first and second data output signals, respectively. This leading edge acceleration stage includes a pull-up buffer having an odd (even) number of inverters therein that are skewed to accelerate the leading edge of the pull-up control pulse relative to a trailing edge of the pull-up control pulse. The leading edge acceleration stage also includes a pull-down buffer having an even (odd) number of inverters therein that are skewed to accelerate the leading edge of the pull-down control pulse relative to a trailing edge of the pull-down control pulse. Accordingly, the pull-up buffer accelerates the clock-to-Q timing when driving Q high and the pull-down buffer accelerates the clock-to-Q timing when driving Q low.

A 2GHz programmable counter with new re-loadable D flip-flop

Abstract: A high-speed programmable counter with a new re-loadable D Flip-flop which integrates the programmable function to a single true-single-phase-clock (TSPC) D flip-flop is presented The proposed re-loadable D flip-flop is able to operate at higher frequencies with lower power consumption in comparison to the performance of the existing bitcell A programmable divide-by-N counter implemented with this re-loadable D flip-flop using the Chartered 018 /spl mu/m CMOS process is capable of operating up to 2 GHz for a 18 V supply voltage with 47 mW power consumption

Drive circuit of semiconductor switching element

Abstract: PROBLEM TO BE SOLVED: To provide a drive circuit of a semiconductor switching element, capable of surely keeping the off-state of the semiconductor switching element and to significantly reduce the through-current, when element is turned on. SOLUTION: A gate sink circuit B2 comprises a comparator CMP that monitors a gate voltage VG of a switching element Q3 to compare it with a prescribed threshold value Vth, a switching element Qs for a sink which is connected between the gate of the switching element Q3 and a ground line, an inverter G2 that inverts the output of the comparator CMP, an inverter G3 for inverting the input signal, an AND circuit G4 for calculating ANDlogic of each output of the inverters G2 and G3, and an RS flip flop FF, in which the output of the AND circuit G4 is inputted as a set signal and the input signal is inputted as a reset signal. COPYRIGHT: (C)2004,JPO&NCIPI

Flip-flop for high-speed operation

Abstract: Provided is a flip-flop capable of operating at high speed by reducing a clock-to-output delay The flip-flop includes a sense amplifier and a latch circuit The sense amplifier includes a first node and a second node, precharges the first node and the second node with a supply voltage according to a state of a clock signal, or receives and amplifies differential input signals according to the state of the clock signal, so as to output differential output signals to the first node and the second node The latch circuit is connected to the first node and the second node, and detects and latches the differential input signals according to the state of the clock signal and the differential output signals The flip-flop described above does not use a NAND gate, so that a clock-to-output delay can be reduced Therefore, the flip-flop has an advantage of operating at high speed

Method and apparatus for determining a processing speed of an integrated circuit

Abstract: A method and apparatus for determining a processing speed of an integrated circuit includes a first flip flop having an input port receiving an input signal, an output port providing a flip flop output signal and a timing port receiving an incoming clock signal. The method and apparatus further includes a delay circuit operably coupled to the output port of the first flip flop, such that the delay circuit receives the flip flop output signal, generating a delayed timing signal. Further included is at least one clock speed adjusting circuit operably coupled to the delay circuit and a multiplexer coupled to the at least one clock speed adjusting circuit and the delay circuit, wherein the multiplexer receives a select delay signal in a selective delay input port. Based on the select delay signal, a multiplexer output signal is chosen and provided to an input port of a second flip flop.

Flip-flop circuit

Abstract: A flip-flop circuit includes a master latch and a slave latch, where a latch operation of the slave latch is controlled by a comparison result between an output signal of the master latch and an output signal of the slave latch. For example, a master latch gate receives an input signal and outputs the input signal under control of a clock signal and an inverted clock signal. A master latch receives the signal output by the master latch gate and latches the signal output by the master latch gate under control of the clock signal and the inverted clock signal. A slave latch gate receives the signal latched by the master latch and outputs the signal latched by the master latch under control of the clock signal and the inverted clock signal. A slave latch receives the signal output by the slave latch gate and latches the signal output by the slave latch gate under control of a slave latch control signal and an inverted slave latch control signal. A comparator receives the signal output by the master latch, an inverted signal of the signal output by the master latch, the signal output by the slave latch and an inverted signal of the signal output by the slave latch, and generates the slave latch control signal and the inverted slave latch control signal.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To provide a flip-flop circuit capable of high-speed operation that can reduce a signal propagation delay time from a switching of a clock signal until its output even for the presence of unsharpened waveform SOLUTION: A data signal received at a data input terminal 1 is given to a closed loop comprising an inverter 10 and a clocked inverter 8 via a clocked inverter 7 and given further to a data transfer element via an inverter 11 An output side of the data transfer element comprising a parallel connection circuit of a P-channel data transfer gate 4 and N-channel data transfer gates 5, 6 is connected to a closed loop comprising an inverter 13 and a clocked inverter 9 and connected to a data output terminal 3 via an inverter 12 An inverted clock signal CB by an inverter 14 or a noninverting clock signal C by inverters 14, 15 is given to each clocked inverter and each data transfer gate

Single-transistor-clocked flip-flop

Abstract: The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

Linear phase detection using two-phase latch

Abstract: Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques.

Semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit (LSI) in which timing design is easily performed, and any timing error is prevented when transferring data between a plurality of the LSI. SOLUTION: This semiconductor integrated circuit is provided with a first flip flop group 13 just after an input port, a second flip flop group 14 just before an output port, a third flip flop group 15 in the circuit, a first clock distributing means 16 for supplying a reference clock to the first flip flop group 13 while making almost constant the delay quantity of the reference clock signal, a second clock distributing means 17 for supplying the reference clock signal to the second flip flop group 14 while making almost constant the delay quantity of the reference clock signal, and a third clock distributing means 18 for supplying the reference clock signal to the third flip flop group 15 while making almost constant the delay quantity of the reference clock signal. In this case, the delay time of the first clock distributing means 16 is set so as to be made larger than the delay time of the third clock distributing means 18, and the delay time of the second clock distributing means 17 is set so as to be made smaller than the delay time of the third clock distributing means 18.

D-type flip-flop with a reduced number of transistors

Abstract: A flip-flop includes a clock signal input, a data signal input, non-inverting and inverting outputs, a data acceptance unit, and a storage unit having a feedback loop with first and second inverter circuits having feedback to one another. The inverting output is coupled to the first inverter circuit output and the non-inverting output is coupled to the second inverter circuit output. The acceptance unit, dependent upon the data and clock signals present, allocates a programming potential to the first or the second inverter circuit input and applies no potential to the respective other input of the circuits. The acceptance unit has a first switching element applying the predetermined programming potential to the input of the first inverter circuit dependent upon the clock and data signals and a second switching element applying the predetermined programming potential to the second inverter circuit input dependent upon the clock and data signals.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To miniaturize a flip-flop circuit SOLUTION: A data holding circuit is formed by inverters G5, G6, the connection point between an output of the inverter G5 and an input of the inverter G6 is rendered operable as a node Q, and the connection point between an output of the inverter G6 and an input of the inverter G5 is rendered operable as a node QN An nMOS transistor M4 driven by a data signal and an nMOS transistor M3 driven by a clock CK2 are connected in series between the node Q and a ground terminal An nMOS transistor M1 driven by an inverted signal of the data signal and an nMOS transistor M2 driven by the clock CK2 are connected in series between the node QN and the ground terminal A minute width pulse generating circuit generates a minute width pulse shorter than the time width of an inputted clock CK1 and supplies it as the clock CK2 COPYRIGHT: (C)2003,JPO

Programmable differential d flip-flop

Abstract: A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source for generating a second bias current, the second current source having programmable inputs for varying the slave cell bias current, thereby controlling the delay of the flip-flop.

Wiring method for clock of semiconductor integrated circuit and semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To provide a wiring method for a clock of a semiconductor integrated circuit that enables a clock buffer for clock skew adjustment that is inserted in a path from a most significant route clock buffer to the end of a flip flop circuit and that can reduce the detour of clock wiring with keeping a hierarchy structure of a layout and the semiconductor integrated circuit thereof SOLUTION: In a step S2, grid-like upper mesh clock wiring is formed on a semiconductor chip In a step S3, a virtual mesh clock terminal is formed on a cross point of the upper mesh clock wiring and the outer shape of a circuit block Then, in a step S4, the upper mesh clock wiring on the circuit block is replaced with lower mesh clock wiring by setting a wiring grid for the mesh clock wiring so as to pass the virtual mesh clock terminal in the circuit block and by changing its property COPYRIGHT: (C)2004,JPO

Flip flop supporting glitchless operation on a one-hot bus and method

Abstract: A flip flop includes a master portion operable to latch at least one of an input signal and an inverted input signal. The flip flop also includes a slave portion operable to latch at least one of the signal latched by the master portion and an inverted signal latched by the master portion in response to a first phase of a clock signal. The slave portion is also operable to be reset in response to a second phase of the clock signal.

Clock-controlled flip-flop has 2 parallel hold stages with common input operated in anti-phase by clock signal, multiplexer with 2 inputs connected to hold outputs, output forming flip-flop output

Abstract: The flip-flop has two parallel hold stages (L1,L2) with a common input signal (D) and operated in anti-phase by the clock signal (CLK) followed by a multiplexer (MUX) with two inputs (A,B) connected to the hold circuit outputs and one output forming the flip-flop output (Q). The multiplexer is controled by the clock signal. At least one of the hold circuits is a static hold circuit. Independent claims are also included for the following: (a) a method of switching a signal through with a flip-flop (b) and a clock-blocking circuit with an inventive flip-flop.