Showing papers on "Flip-flop published in 2004"

Superconductor integrated circuit fabrication technology

Abstract: Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates/cm/sup 2/. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for a static divider (toggle flip-flop) have been demonstrated. Large digital logic circuits, with Josephson junction counts greater than 60 k, have also been fabricated using advanced foundry processes. Circuit yield is limited by defect density, not by parameter spreads. The present level of integration is limited largely by wiring and interconnect density and not by junction density. The addition of more wiring layers is key to the future development of this technology. We describe the process technologies and fabrication methodologies for digital superconductor integrated circuits and discuss the key developments required for the next generation of 100-GHz logic circuits.

Online BIST and BIST-based diagnosis of FPGA logic blocks

Abstract: We present the first online built-in self-test (BIST) and BIST-based diagnosis of programmable logic resources in field-programmable gate arrays (FPGAs). These techniques were implemented and used in a roving self-testing areas (STARs) approach to testing and reconfiguration of FPGAs for fault-tolerant applications. The BIST approach provides complete testing of the programmable logic blocks (PLBs) in the FPGA during normal system operation. The BIST-based diagnosis can identify any group of faulty PLBs, then applies additional diagnostic configurations to identify the faulty look-up table or flip-flop within a faulty PLB. The ability to locate defective modules inside a PLB enables a new form of fault-tolerance that reuses partially defective PLBs in their fault-free modes of operation.

Semiconductor integrated circuit

Abstract: A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to the first data path for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal. One of the logic circuits receives data from the first flip flop and another logic circuit outputs output data. The second flip flop is connected between the logic circuits for transferring signal between them in response to the reference clock signal. The third flip flop is connected to another logic circuit for outputting the output data in response to a second clock signal that is advanced from the reference clock signal. The second data path transfers data received from the third flip flop.

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology

Abstract: 80-Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology, which has a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. The circuit was designed with differential operation based on source-coupled FET logic (SCFL). To overcome deterioration of the 80-GHz clock signals in a single-ended to differential signal converter in the input buffer, a rat-race circuit was used as a converter. Measurements showed that the circuit achieved a gain of over 2 dB higher than a conventional converter using a differential pair circuit, and power consumption was reduced from 380 to 260 mW. The power supply voltage was -5.7 V, and total power consumption was 1.2 W. Since there is no commercially available 80-Gbit/s-pulse pattern generator, we developed a selector module to measure the D-FF. These measurements showed that the D-FF successfully operated at 80 Gbit/s, which is almost twice the speed reported to date.

A low power 13-Gb/s 2/sup 7/-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS

Abstract: We present a pseudo random bit sequence (PRBS) generator with a sequence length of 2/sup 7/-1. The circuit uses a 7 bit full rate shift register with a linear XOR feedback and works up to data rates of 13 Gb/s. The PRBS generator features a divide by 2 trigger divider, two 3 bit shifted outputs and an autostart logic. The circuit draws 137 mA from a single 1.5 V supply. The circuit is manufactured in 120 nm bulk CMOS technology.

A novel ultra high-speed flip-flop-based frequency divider

Abstract: Frequency dividers play an important role in high speed communications systems. In particular, optical communication circuits demand frequency dividers capable of operating well above 10 GHz. This paper presents a high-speed flip-flop-based frequency divider incorporating a new high-speed latch topology, which provides satisfactory performance for frequencies up to 17 GHz. This circuit is designed and simulated in a standard 0.18 /spl mu/m CMOS process.

Scan flip flop, semiconductor device, and production method of semiconductor device

Abstract: There is provided a flip flop circuit with a scan structure which is formed by an input section of a dynamic circuit and an output section of a static circuit wherein data is taken in within an interval of a short pulse width as compared with a clock cycle. In the dynamic circuit of the input section, the number of serially-connected MOS transistors to which a data signal is input is smaller than the number of serially-connected MOS transistors to which a test input signal is input. With this structure, the speed of operation is increased at the time of data storage for a data signal input, and the number of MOS transistors is reduced.

CMOS master/slave flip-flop with integrated multiplexor

Abstract: A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To provide a flip-flop circuit which is suitable for a high-speed operation and can prevent influence by a change in an operation environment and realize a stable operation in a wide range operating condition SOLUTION: In a pulse generation circuit 10A, when a clock signal CK is on a low level, a transistor TPO precharges a node N2 on a high level, a negative pulse signal S1 is generated according to the leading edge of the clock signal CK, a transfer gate TG1 conducts in accordance with the negative pulse signal S1, and input data is obtained by a storage node N4 of a latching circuit 20, and when a coincidence detection circuit 11 or 12 detects that the input data coincides with held data of the latching circuit, the node N2 is discharged to end a negative pulse, the transfer gate TG1 is interrupted by the end of the negative pulse to make a TG0 conduct to therefore hold data obtained by the latching circuit 20 COPYRIGHT: (C)2005,JPO&NCIPI

A 2.5-V, 40-Gb/s decision circuit using SiGe BiCMOS logic

Abstract: A 40-Gb/s decision circuit is reported which operates from a 2.5-V supply. It includes a flip-flop, a broadband transimpeclance preamplifier, a tuned 40-GHz clock buffer, and a 50-/spl Omega/ output driver. The flipflop features a novel BiCMOS CML logic topology, which allows for lower supply voltages as compared with pure bipolar implementations without compromising speed. A mm-wave transformer is used to perform single-ended-to-differential conversion along the 40 GHz clock path.

A novel CMOS double-edge triggered flip-flop for low-power applications

Abstract: A novel low-power double-edge triggered flip-flop is presented in this paper. Low-power and high-speed flip-flops are required in many applications, especially in SoC systems. Double-edge triggered flip-flop can latch the data signal changes both from high to low and low to high. Thus, lower clock frequency is used while the data throughput is preserved. The proposed flip-flop uses a low-swing clock technology and low-Vt transistors for the clock transistors to reduce the leakage current problem. Beside, only a single latch is used and lower power consumption is achieved. HSPICE simulation results show that the power dissipation of the proposed flip-flop is reduced by at least 28% and the power-delay product is also reduced by at least 50%.

Novel all-optical flip-flop using semiconductor optical amplifiers in innovative frequency-shifting inverse-threshold pairs

Abstract: All-optical digital sequential logic reduces the expense and bit rate constraints associated with optical-electronic-optical (OEO) conversion in telecommunications. Two semiconductor optical amplifiers (SOAs) are directly coupled by connecting the output of each to the input of the other. This new configuration provides positive feedback to create a logical NOT or inverse for complete logic. An inverted optical threshold improves the quality of bit modulation. At the same time, frequency shifting allows improvement in the quality of the optical carrier. The SOA pair is analyzed in closed form to show that the positive feedback provides an output-input slope steeper than –1, allowing connection of two pairs to form a flip-flop. Two SOA pairs are cross-connected by connecting the output of each pair to the input of the other, to construct a novel R-S flip-flop. Closed form analysis shows, for the first time, that there is an unstable state and two stable states forming bistability for this configuration. Simulation demonstrates setting and resetting the reset-set (R-S) flip-flop at more than 5 Gbps. Agreement between closed form analysis and numerical simulation provides verification of the validity of the results obtained.

Latch circuit and flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To provide a latch circuit that operates at high speed with a low voltage, and so on. SOLUTION: The present invention comprises a transmission gate 5, an inverter circuit 6, a capacitor C2 for storing data, and a clocked inverter circuit 9. A threshold voltage of an MOS transistor comprising the transmission gate 5 is made relatively higher than that of an MOS transistor comprising the clocked inverter circuit 9. When a clock signal CK is in an H level, the transmission gate 5 is turned on to pass input data, stored data in the capacitor C2 are updated, the inverter circuit 6 inverts out the updated data, and the clocked inverter circuit 9 is turned on to invert out the input data. When the clock signal CK is in an L level on the other hand, the transmission gate 5 is turned off, the capacitor C2 holds the stored data, the inverter circuit 6 inverts out the stored data, and the clocked inverter circuit 9 stops outputting. COPYRIGHT: (C)2006,JPO&NCIPI

Flip-flop circuit and shift register

Abstract: PROBLEM TO BE SOLVED: To reduce a layout area, and to reduce power consumption in the transition of a clock signal by reducing the number of MOS transistors of a flip flop circuit. SOLUTION: A P channel MOS transistor 11 and an N channel MOS transistor 12 respectively connected to an internal normal rotation clock node ck and an internal inversion clock node ckb are shared by a try state inverter 1 included in a master latch and a try state inverter 5 included in a slave latch. COPYRIGHT: (C)2004,JPO

Method and apparatus of retaining maximum speed of flip-flop metastability based random number generators

Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.

Turning off clock to flip flops

Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

Two-latch clocked-LSSD flip-flop

Abstract: A clocked level-sensitive scan design may have flip-flops designed to have data, scan-in, and output ports and to utilize two clock signals. Such a clocked level-sensitive scan flip-flop may be built utilizing two latches.

High speed semi-dynamic flip-flop circuit

Abstract: A high-speed semi-dynamic flip-flop circuit uses a keeper transistor to replace the back-to-back inverter keeper circuit of prior art semi-dynamic flip-flop circuits to avoid the fight between a first node, or OUTBAR node, and the prior art back-to-back inverter keeper circuit. The result is a faster semi-dynamic flip-flop circuit that is also immune to noise.

Strobe signal delay device and semiconductor device equipped with the same

Abstract: PROBLEM TO BE SOLVED: To eliminate delay to a flip flop of a strobe signal corrected by a delay element and its variation in an interface part of a data reception device for use in a DLL. SOLUTION: In a delay device, a delay element having a variable delay value and a delay control circuit for controlling delay of the delay element are provided, and an output of the delay element and an output of a minimum delay element which has a delay value being a minimum delay unit of the delay element are connected to a phase comparator, and the delay element and the minimum delay element have a common input, and the strobe signal or a reference clock is selected as the common input, and the delay control circuit can be controlled by a comparison result of the phase comparator, and the output of the delay element can be used as a clock of a plurality of data latches. COPYRIGHT: (C)2006,JPO&NCIPI

Master latch circuit with signal level displacement for a dynamic flip-flop

Abstract: A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK), resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) and which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (ClkDELAY) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage .

Nonvolatile flip-flop circuit, and method for driving the same

Abstract: A method for driving a nonvolatile flip-flop circuit, comprising a data hold step in which a first clocked inverter (604), a second clocked inverter (603) and a third switching element (602) are on-state, a first switching element (605), a second switching element (607) and a third clocked inverter (608) are off-state, and a data signal (D) is inputted, whereby the ferroelectric polarization of a ferroelectric gate transistor (601) is utilized to hold the input data signal (D); and a data output step in which the first clocked inverter (604), the second clocked inverter (603) and the third switching element (602) are turned off, the first switching element (605), the second switching element (607) and the third clocked inverter (608) are turned on, whereby the application of the data signal (D) is cut off and the ferroelectric polarization of the ferroelectric gate transistor (601) is maintained, so that output signals Q(-Q) are outputted based on the held data signal (D).

System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator

Abstract: A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.

Low power flip-flop circuit

Abstract: PURPOSE: A low-power flipflop circuit is provided to reduce the power consumption by removing a switching operation between an output buffer and an internal clock generation circuit when an input signal of a flipflop is not changed CONSTITUTION: A low-power flipflop circuit includes a latch, a comparison circuit(430) and an internal clock generation circuit(440) The latch is used for receiving and maintaining an input signal according to an internal clock signal The comparison circuit(430) is used for comparing the input signal to an output signal of the latch The internal clock generation circuit(440) is used for receiving an external clock signal and generating an internal clock signal The internal clock generation circuit is used for controlling a path of the external clock signal, generating the delayed and inverted external clock signal, and generating the internal clock signal The internal clock signal is generated by performing a NAND operation for the external clock signal and the delayed and inverted external clock signal The internal clock signal is synchronized with the external clock signal

Resonant tunnelling diode based QMOS edge triggered flip-flop design

Abstract: Resonant tunnelling diode (RTD) is well known as an ultra-fast device due to small intrinsic capacitance, large drive current was well as the high switching speed. Pair of RTDs has self-latching property, which makes RTD a very promising candidate for nano-pipelining circuit design. The most pervasive used RTD-based sequential logic is MOBILE. However, MOBILE is a return-to-zero mode circuit, which makes it difficult to be used in some specific applications. In this paper, we proposed three quantum MOS (QMOS) flip-flop designs. Our designs explore the advantage of MOBILE while keeping the output to a holding stage instead of return-to-zero. The circuit topologies and circuit operations are described and discussed. The performance of these circuits is evaluated by using HSPICE. Then the final results are compared with each other.

Flip-flop circuit having majority decision logic circuit

Abstract: A flip-flop circuit having a majority decision logic circuit which, even if a software error occurs, remedies the error, holds and outputs the correct content stored, has a small circuit scale, and is easily tested. The flip-flop circuit comprises multiple master latches for writing an input signal, a majority decision logic circuit having inputs connected with the outputs of the master latches, a slave latch having an input connected with the output of the majority decision logic circuit and having an output connected with the input of the majority decision logic circuit. During a period when the master latches write no input signals, the output of the majority decision logic circuit is supplied to the inputs of the master latches.

Mtcmos flip-flop circuit capable of retaining data in sleep mode

Abstract: PURPOSE: A MTCMOS flipflop circuit for storing data in a slip mode is provided to maintain a state prior to a slip mode in a switching process of the slip mode to an active mode by adding a feedback circuit to an existing flipflop circuit to utilize only a slip mode control signal. CONSTITUTION: A MTCMOS flipflop circuit for storing data in a slip mode includes a master latch and a slave latch to receive, latch, and output input data according to an internal clock signal. An output of the MTCMOS flipflop circuit is in the state prior to the slip mode in a switching process of the slip mode to an active mode by forming and storing a data state of an input terminal of the master latch corresponding to a data inverting state of an input terminal of the slave latch in the slip mode. The MTCMOS flipflop circuit further includes a switching transistor connected between the virtual ground and the ground. The switching transistor is turned on by a slip mode control signal in the slip mode. In addition, the switching transistor is turned off by the slip mode control signal in an active mode.

Signal control circuit and image formation device

Abstract: PROBLEM TO BE SOLVED: To make it possible to realize a normal output of PWM signal by an inexpensive means. SOLUTION: One side of the two PWM formation circuits, which are installed in an image formation device 100 such as high-speed copying machines carrying out the simultaneous luminescence of the two beams, forms two or more retarding signals of different delay time from the PWM signal P02 output from the other PWM formation circuit by a delay circuit 32 at a test mode. By detecting the retarding signal synchronizing with the reverse signal of the PWM signal P02 output from the other PWM formation circuit among two or more retarding signals formed by the delay circuit according to a retarding-quantity measuring circuit 33, the pulse width of the PWM signal P02 is measured, and the measured result of the retarding-quantity measuring circuit 33 is preserved by a FF(Flip Flop)34. COPYRIGHT: (C)2005,JPO&NCIPI

Automatic design system and automatic design method

Abstract: PROBLEM TO BE SOLVED: To provide an automatic design system and an automatic design method which can efficiently reduce the power consumption while preventing the extension of the area of a semiconductor chip such as an LSI and also shortening a design period of time. SOLUTION: The automatic design system is provided with an input device 1 for inputting circuit information of a logic circuit for use in pattern layout of an LSI, a glitch retrieval part 21 for retrieving a circuit element where glitch occurs, a skew calculation part 22 for calculating a skew of a clock signal inputted to a clock input end of a flip flop (F/F) which outputs a signal to input ends of circuit elements, a circuit information analysis part 21 for analyzing whether glitch can be reduced or not by setting the skew as a first target skew, a first target skew setting part 32a for setting the first target skew if an analysis result indicating that glitch can be reduced, and a first latch insertion part 33a for inserting a first latch in the case of an analysis result indicating that glitch cannot be reduced. COPYRIGHT: (C)2004,JPO

Flip flop especially a D flip flop for high frequency uses has clock and data signal inputs and inverted and non inverted outputs

Abstract: A flip-flop has inputs (3,4) for clock (CLK) and data (D) signals, an inverted (QN) and a non-inverted (Q) output and comprises two holding elements (1b,2b) with back coupling loops comprising nodes (K1,K2) which are coupled together and receive the inverted and non-inverted signals.