Showing papers on "Flip-flop published in 2005"

All-optical flip-flop based on a single SOA-MZI

Abstract: A novel architecture of an all-optical flip-flop is proposed. The architecture is comprised of a single semiconductor optical amplifier-based Mach-Zehnder interferometer with a feedback loop. The simulation results show that low switching energies (<2-pJ pulses) and fast operation (<1-ns response delays) may be achieved.

A beginning in the reversible logic synthesis of sequential circuits

Abstract: This paper provides the initial threshold to building of more complex system having reversible sequential circuits as a primitive component and which can execute more complicated operations using quantum computers. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. The important reversible gates used for reversible logic synthesis are Feynman Gate, New Gate and Fredkin gate. The novelty of the paper is the reversible designs of Flip Flops. The Flip Flops that are synthesized using reversible logic are RS Flip Flop, JK Flip Flop, D Flip Flop, T Flip Flop and Master Slave Flip Flop

A novel high-speed sense-amplifier-based flip-flop

Abstract: A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.

Radiation-induced clock jitter and race

Abstract: The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft error rate (SER) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SER if no mitigation techniques are applied. Our results show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20/spl times/ improvement in sequential SER as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty.

Flip-flop circuit having low power data retention

Abstract: A flip-flop ( 10 ) has a normal mode and a low power mode to save power. The flip-flop ( 10 ) has a master latch ( 14 ) and a slave latch ( 20 ). The slave latch ( 20 ) is used to retain the condition of the flip-flop ( 10 ) during the low power mode, where power is withdrawn from the master latch ( 14 ) but maintained on the slave latch ( 20 ). The slave latch ( 20 ) may use transistors with lower leakage characteristics than the transistors that make up the master latch ( 14 ). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop ( 10 ) is maintained by implementing the slave latch ( 20 ) so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch ( 20 ) has an input/output terminal to tap into the signal path between the master latch and an output circuit ( 22 ).

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

Abstract: A 45-Gb/s BiCMOS decision circuit operating from a 2.5-V supply is reported. The full-rate retiming flip-flop operates from the lowest supply voltage of any silicon-based flip-flop demonstrated to date at this speed. MOS and SiGe heterojunction-bipolar-transistor (HBT) current-mode logic families are compared. Capitalizing on the best features of both families, a true BiCMOS logic topology is presented that allows for operation from lower supply voltages than pure HBT implementations without compromising speed. The topology, based on a BiCMOS cascode, can also be applied to a number of millimeter-wave (mm-wave) circuits. In addition to the retiming flip-flop, the decision circuit includes a broadband transimpedance preamplifier to improve sensitivity, a tuned 45-GHz clock buffer, and a 50-/spl Omega/ output driver. The first mm-wave transformer is employed along the clock path to perform single-ended-to-differential conversion. The entire circuit, which is implemented in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe HBT, consumes 288 mW from a 2.5-V supply, including only 58 mW from the flip-flop.

Ultra low area overhead retention flip-flop for power-down applications

Abstract: In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

Digital design component with scan clock generation

Abstract: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of delay buffers in the scan mode data paths. Resulting application circuits have reduced circuit area, power consumption and noise generation. A clock generator for scan mode clocking is provided to obtain the separate, non-overlapping scan mode clocks. Scan mode clocks may be generated with a toggle flip flop, a pulse generator or a clock gating circuit.

Implementation of tristate logic based all optical flip-flop with nonlinear material

Abstract: The advantages of multivalued logic in optical parallel computation need no introduction. There are lots of proposals, already reported, where tristate, quarternary state logic operations can be performed with optics. Here we report a new approach to implement tristate logic based all optical flip-flop using optical nonlinear material. The concept and the principle of operation of this type of flip-flop are different from that of the conventional binary one.

An All-Optical R-S Flip-Flop by Optical Non-Linear Material

Abstract: In optical parallel computation the super fast switching speed is very much expected from the switching devices within the computer architecture. Several approaches were proposed in last few decades around the world where uses of non-liner and photo-refractive materials were seen massively in the purpose of developing switching devices. By the proper use of non-linear material logical operations (like NAND, AND, NOT, EX-OR gate) can be performed. These operations are all optical in nature. In this paper such an optical system is proposed which is capable to follow the truth table of a R-S flip-flop. Optical NAND and NOT gate are used here as basic building block.

MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop

Abstract: A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop, a circuit including the MTCMOS flip-flop, and a method of forming the MTCMOS flip-flop are disclosed. The MTCMOS flip-flop breaks a leakage current path during a sleep mode to retain an output data signal. The MTCMOS flip-flop typically further uses a data feedback unit to retain the output data signal.

Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-/spl mu/m CMOS technology

Abstract: The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-/spl mu/m CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm/sup 2/. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.

Semiconductor integrated circuit device having scan flip-flop circuit

Abstract: A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.

Asymmetric precharged flip flop

Abstract: A flip-flop circuit includes a differential stage coupled to a latch stage. The differential stage comprises cross-coupled dynamic logic and only provides a single output to the latch stage. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either an output side or reference side of the differential stage is discharged. Also, during the evaluation phase, the latch stage write port is enabled while feedback is disabled, and the flip flop thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the latch stage write port is disabled and feedback is enabled, thereby retaining its present state. Only a single side of the differential stage is used to drive the latch stage and the differential stage may be implemented in an asymmetric fashion.

Error-detection flip-flop

Abstract: An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.

Design of 3-valued r-s & d flip-flops based on simple ternary gates

Abstract: Design of 3-valued R-S & D type of flip-flops is described. A new clock is developed according to which circuit makes transition as well as retains present, past & former past information. The proposed flip-flops are constructed using clocked T-Gates that reduces the number of transistors required to implement single clocked gates. In the verification by simulation, the proposed flip-flops appears to have lesser power consumption and better speed of operation.

High-speed flip-flop circuit

Abstract: A flip-flop circuit that captures an input signal in sync with a clock, has a first gate outputting a first signal corresponding with input signal; a second gate generating a second signal of a first predetermined level in response to a first level of clock and causing the second signal to be a level of first signal in response to a second level of clock; and a third gate outputting a third signal of second signal in response to the second level of clock. Further the flip-flop circuit has a first inversion feedback circuit between the third and second signal terminals, that is activated in response to the second level of clock and latches the third signal together with third gate; and level fixing circuit that fixes the first signal terminal at a second predetermined level with a time delay after the clock changes to the second level.

Flip flop circuit and apparatus using a flip flop circuit

Abstract: A flip flop circuit includes a first latch circuit which latches an input data at a leading edge of a clock signal, a second latch circuit which latches the input data at a trailing edge of the clock signal, and a selector which, during a period from the leading edge to the trailing edge of the clock signal, selects an output data from the first latch circuit, and during a period of the trailing edge to a next leading edge of the clock signal, selects an output data from the second latch circuit, in which one of the first latch circuit and the second latch circuit functions as a master latch circuit for receiving a scan data during a scan mode, and the other of the first latch circuit and the second latch circuit functions as a slave latch circuit for latching data outputted from the master latch circuit.

Chaos-based computation via Chua's circuit: parallel computing with application to the SR flip-flop

Abstract: This paper deals with chaos-based computing, that is, the exploitation of chaos to do flexible computations. In particular, this paper illustrates the parallel implementation of two combinatorial logic gates using a single Chua's circuit. Furthermore, a novel chaos-based sequential gate that behaves like the SR flip-flop is introduced.

Scan flip-flop circuit with reduced power consumption

Abstract: A scan flip-flop circuit and related scan chain are disclosed. The scan flip flop comprises in one embodiment an input stage receiving, selecting between, and outputting either a normal logic signal or a scan logic signal in accordance with an operation mode for the scan flip-flop circuit. The scan flip-flop further comprises a flip-flop receiving either the normal logic signal or the scan logic signal selected by the input stage, and outputting in accordance with a clock signal a first logic signal from a first flip-flop output terminal and an output stage receiving the first logic signal and comprising first and second output terminals, such that a signal output from the first output terminal is identical to the normal logic signal received in the input stage, and a signal output from the second output terminal maintains a high logic value when the scan flip-flop circuit operates in a normal mode and a signal output from the first and second output terminals are identical to the scan logic signal received in the input stage when the scan flip-flop circuit operates in a scan mode.

Slack borrowing in flip-flop based sequential circuits

Abstract: In this paper, we have modelled the flip-flop clock to output delay dependency on the data arrival time and introduced this phenomenon in timing analysis. Traditionally, finding the minimum clock period of a flip-flop based sequential design was based on the assumption that the setup-time and clock to output delay of a flip-flop are constant and hence each stage of the pipeline can be analyzed independently. However, it is well known that the delay of a flip-flop depends on the data arrival time at its input and hence there exists an interdependence among different pipeline stages. The problem of finding the minimum clock period of such a coupled system is a non-trivial problem. In this paper, we formu-late the problem of finding the minimum clock period of a flip-flop based sequential circuit accounting for these dependencies. We show that the problem is a non-linear convex optimization problem. We propose three different solution approaches and compare their results on ISCAS '89 sequential benchmark circuits. Modeling these data arrival time dependencies we have seen a consistent decrement of approximately 50-60ps compared to the traditional approach using constant setup-time and flip-flop delays. We also show how the analysis can be extended to account for hold time constraints for short paths in the circuit.

Control signal generator, latch circuit, flip flop and method for controlling operations of the flip-flop

Abstract: A control signal generator, latch circuit, flip-flop and method for controlling operations in the flip-flop may be configured so as to efficiently perform latching and scanning operations in the flip-flop. The control signal generator may generate at least two pulses based on a scan enable signal being received in a first state and on a received clock signal, and may generate at least two internal clock signals based on the received clock signal, and based on the scan enable signal being received in a second state. The latch circuit may latch a received input signal based on the at least two pulses and may latch a received scan input signal based on the at least two internal clock signals.

Hybrid latch flip-flop

Abstract: A hybrid latch flip-flop is applied to an LCD. The hybrid latch flip-flop includes a negative pulse generation unit, a latch flip-flop, and a buffer unit. The latch flip-flop includes a sampling unit and a hold unit. One feature of the present invention is that fewer transistors are employed in the hybrid latch flip-flop, which gives rise to low power consumption. Another feature of the present invention is that, by employing the negative pulse generation unit of a double edge trigger type, the data processing capacity of the hybrid latch flip-flop is doubled without changing the clock frequency.

Gate driving circuit for semiconductor device

Abstract: PROBLEM TO BE SOLVED: To surely prevent an excessive current at turn off of a small current. SOLUTION: A gate driving circuit 20 is supplied with a control signal Sa via an insulator 10, and the junction between gate resistors 13 and 15 is connected to the gate of an IGBT5a. The gate driving circuit 30 is composed of a reference power source 31 for setting a first reference value Vref1, a comparator circuit 32 which compares this first reference value Vref1 with the gate potential of an IGBT5a, an AND circuit 33 which performs the AND operation between the output of this comparator circuit 32 and the switching signal S2 for switching on or switching off a switch circuit 14, and a flip flop 34 which has a set terminal (S) and a reset terminal (R). It operates to switch on the switch element 22 and keep it after the control signal Sa to the gate driving circuit 20 is switched into an OFF command. COPYRIGHT: (C)2007,JPO&INPIT

Flip-flop circuit having majority-logic circuit

Abstract: A flip-flop circuit having a majority-logic circuit is disclosed. The circuit further includes multiple master latches for writing in corresponding input signals, and one slave latch having an input connected to an output of the majority-logic circuit and an output connected to the inputs of the majority-logic circuit. The majority logic-circuit has multiple inputs connected to respective outputs of the master latches. During the period in which the master latches do not write in the corresponding input signals, an output signal of the majority-logic circuit is supplied to respective inputs of the master latches.

Dual data rate flip-flop

Abstract: A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-flop outputs data on either the rising or falling edges of the applied clock. In the double data-rate mode, when a first latch disposed in the flip-flop operates in a sampling mode, the second latch disposed in the flip-flop operates in a holding mode to supply the output data, and when the second latch operates in the sampling mode, the first latch operates in the holding mode to supply the output data. Accordingly, with each of the rising or falling edge of the clock, one of the latches supplies an output data.

Resonant Tunneling Diode/HBT D-Flip Flop ICs Using Current Mode Logic-Type Monostable-Bistable Transition Logic Element with Complementary Outputs

Abstract: A current mode logic (CML)-type resonant tunneling diode (RTD)/heterojunction bipolar transistor (HBT) monostable-bistable transition logic element (MOBILE) IC with complementary outputs is proposed, which can simplify logic designs on the basis of complementary logic operation. Using the CML-type current modulator in the MOBILE IC, both the noninverted and inverted outputs are simultaneously generated with a single input signal. The CML-type MOBILE IC with complementary outputs has been fabricated using an InP-based RTD/HBT technology, and the operation of the fabricated circuit has been confirmed up to 10 Gb/s as a MOBILE with the complementary outputs. Moreover, the operation of a non-return-to-zero (NRZ) D-flip flop circuit, integrated with a set/reset latch (SR latch) using the CML-type complementary MOBILE IC has been for the first time confirmed up to 8 Gb/s with a low power consumption of 86 mW.

A novel 40-GHz flip-flop-based frequency divider in 0.18/spl mu/m CMOS

Abstract: This paper presents a 40GHz flip-flop-based frequency divider incorporating a latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode, to speed up the latch operation and to increase the driving capability. The proposed frequency divider performs at 40GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18/spl mu/m SiGe BiCMOS process provided by Jazz Semiconductor, where only CMOS transistors were used. It draws 5mA current from a 1.8V supply voltage.

Flip-flop circuit arrangement and method for processing a signal

Abstract: A flip-flop circuit arrangement and an associated method are disclosed, wherein a changeover between a master and a slave block is not effected by switching on and switching off respective current sources, but rather by impressing a compensation current that effects the changeover. One or more aspects of the present invention make it possible to reduce a supply voltage and at the same time, on account of low parasitic capacitances of the circuit, to provide a frequency divider in the gigahertz range which can be integrated using MOS circuit technology.

System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop

Abstract: The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.