Showing papers on "Flip-flop published in 2006"

All-optical flip-flop circuit composed of coupled two-port resonant tunneling filter in two-dimensional photonic crystal slab.

Abstract: We propose an optical flip-flop circuit composed of two-port resonant-tunneling filters based on a two-dimensional photonic crystal slab with a triangular air-hole lattice. This circuit can function as an optical digital circuit that synchronizes input data with a clock. In this report, we demonstrate that this circuit can achieve a fast operating speed with a response time of about 10 ps and a low operating power of 60 mW by employing a two-dimensional FDTD calculation.

An Area and Power Efficient Radiation Hardened by Design Flip-Flop

Abstract: A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm2 /mg) at VDD=1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are described

Efficient Building Blocks for Reversible Sequential Circuit Design

Abstract: Reversible logic is gaining interest in the recent past due to its less heat dissipating characteristics. It has been proved that any Boolean function can be implemented using reversible gates. In this paper we propose a set of basic sequential elements that could be used for building large reversible sequential circuits leading to logic and garbage reduction by a factor of 2 to 6 when compared to existing reversible designs reported in the literature.

A non-volatile flip-flop in magnetic FPGA chip

Abstract: In this paper, the authors propose a non-volatile flip-flop, which presents simultaneously low power dissipation and high speed. This flip-flop is based on MRAM (magnetic RAM) technology on standard CMOS. In this non-volatile flip-flop design, the authors use magnetic tunnel junctions (MTJ) as storage element. Contrary to the complex sense amplifier circuit in standard MRAM circuits, a simple one based on SRAM cell is used to couple with two MTJs per bit in magnetic logic circuit. The flip-flop works exactly as a classical flip-flop hut the information is stored simultaneously in the two MTJs, which makes this flip-flop non-volatile. As the writing frequency has a strong impact on the power consumption, the MTJ writing frequency is designed to be defined by the users depending on different usage. During the startup or reset phase, the flip-flop master stage is used as the MTJ sense amplifier and the flip-flop is initialized to the previously stored state in about 200 ps. This figure has been demonstrated by electrical simulation on a 90 nm CMOS technology and with a complete and precise MTJ model

Logic SER reduction through flip flop redesign

Abstract: In this paper, we present a new flip flop sizing scheme that efficiently immunizes combinational logic circuits from the effects of radiation induced single event transients (SET). The proposed technique leverages the effect of temporal masking by selectively increasing the length of the latching windows associated with the flip flops thereby preventing faulty transients from being registered. We propose an effective flip flop sizing scheme and construct a variety of flip flop variants that function as low-pass filters for SETs and reduce the soft error rates (SER) of combinational circuits. In contrast to previously proposed flip flop designs that rely on logic duplication and complicated circuit design styles, our method provides a simple yet highly effective mechanism for logic SER reduction while incurring very small overheads in both delay (about 5 FO4) and power (about 5%). Experimental results at the circuit level on a wide range of benchmarks show 1000/spl times/ reductions in SER for small increases in circuit delay and power.

Flip-flop and semiconductor integrated circuit

Abstract: A flip-flop is disclosed which includes: a clock supply circuit configured to output or fix a clock signal alternating between two predetermined states in accordance with a sleep signal; a first holding circuit configured to fetch or hold an input signal in accordance with a state the clock signal indicates; a second holding circuit configured to fetch or hold a first signal output by the first holding circuit in accordance with a state the clock signal indicates; an input switching circuit configured to supply as the input signal a second signal output by the second holding circuit or to supply an external signal as the input signal in accordance with the hold signal; and a power supply control circuit configured to supply or not to supply power to the first holding circuit and the input switching circuit in accordance with a power supply control signal.

Soft error tolerant flip flops

Abstract: A register designed to detect and correct soft errors in real time A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches The content of these multiple latches are fed to a majority voting circuit If the content of any of these latches is corrupted by soft error, it is filtered out through the majority voting circuit and correct data is passed out from the output of the flip flop In one embodiment, this design operates as a simple scan flip flop or scan-hold flip flop, and is useful for system testability purposes

Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic

Abstract: With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address single even upsets (SEUs). Robust combinational logic designs capable of tolerating single event transients (SETs) also are needed in lower technology nodes. In this paper, we present a novel SET mitigation scheme for flip-flops based on the time redundancy principle. The incurred area overhead due to the radiation hardening is minimized by reusing existing components (uses existing scan portion for SET tolerance). As shown by the simulation results, the proposed SET tolerant flip-flop has no performance overheads and simulation results that show the area overheads in ISCAS benchmark circuits are also presented.

A 40-GHz Flip-Flop-Based Frequency Divider

Abstract: This brief presents the design and implementation of a 40-GHz flip-flop-based frequency divider which incorporates a novel latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode. The proposed topology will speed up the latch operation and increase the driving capability. It is capable of performing frequency division at 40 GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18-mum SiGe BiCMOS process, where only CMOS transistors were used. It draws an average current of 5 mA from a 1.8-V supply voltage

D flip-flop

Abstract: A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.

XNOR-based double-edge-triggered flip-flop for two-phase pipelines

Abstract: The conventional approach of double-edge-triggered flip-flops (DET-FFs) is to have two similar edge-triggered latches. And the achieved faster speed is at the cost of double chip area and complex logic structure. By contrast, the XNOR-based approaches is difficult to reach the speed demand due to the delay of the XNOR -based clock generator. This paper proposes a new designed DET-FF based on an alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage, we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following the pulse-generator acts as an XNOR-based DET-FF, which accomplishes the almost same speed and less power dissipation as compared with two conventional DET-FFs under HSPICE simulation. We also implemented the XNOR-based DET-FF in a two-phase-pipeline system, and the HSPICE simulation in the TSMC 0.25 um CMOS process shows our proposed DET-FF is much faster than those two conventional DET-FFs.

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

Abstract: Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps

Hybrid Integrated, All-optical Flip-flop Memory Element for Optical Packet Networks

Abstract: We describe a novel, fully-packaged, hybrid-integrated all-optical flip-flop memory element. Static state contrast ratios of 10dB and 13dB are demonstrated and the flip-flop can have its state changed dynamically every 32ns with the introduction of state-setting pulses (pulse widths ≪150ps).

Chaos-based sr flip–flop via chua's circuit

Abstract: This Letter contributes to the topic of chaos computing by introducing a new chaos-based implementation of sequential gates. In particular, the early results reported herein show that a chaos-based SR flip–flop can be obtained from two cross-coupled NOR gates implemented by a single Chua's circuit.

A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems

Abstract: A pulse-triggered D flip-flop with an embedded clock-gating scheme that is suitable for low-power high-speed synchronous applications is presented in this paper. Various flip-flops and different proposed clock-gating circuits were simulated to determine and compare their performance in terms of speed and power dissipation, in order to obtain the best featured one. The circuits were designed using a 0.35 mum CMOS technology and supplied with 3.3 V. As shown in HSPICE simulations, the proposed flip-flop operates up to 1.25 GHz with a delay of 0.3 ns and a power dissipation of 4.1 mW, and it leads to power savings around 45% when used to build a 16-bits binary counter, compared to the counter that uses the non-gated version of the pulse-triggered flip-flop

Single-event effect tolerant latch circuit and flip-flop circuit

Abstract: Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop

Abstract: In this paper, we propose two novel dual edge-triggered flip-flops. One design eliminates redundant transitions of internal nodes when current data is the same as the previous one. This has the least power delay product compared to other dual edge-triggered flip-flops in all range of possible data switching activity and its delay is also the smallest. The other proposed flip-flop disables internal clocked transistors. When data switching activity is within 20%, it has the least power consumption.

Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures

Abstract: Low power consumption and radiation hardness are generally competing requirements for space electronics as well as many Earth-bound high reliability applications. Fault tolerance typically requires redundancy and reconfigurability to ensure correct functional operation in the presence of errors. However, this runs contrary to the requirement for reduced power consumption in many battery-powered applications. Recently, subthreshold logic has emerged as a technology that delivers the theoretical minimum energy per computation by running at ultra-low voltages. For many applications, the resulting performance degradation is tolerable due the dramatic increase in energy efficiency. Beyond the concerns with performance, an additional challenge is related to radiation hardness and noise immunity. The marriage of subthreshold logic and reconfigurable, high-reliability electronics is inevitable, yet there has been to date no investigation of the effects of radiation on circuits that operate at such low voltages. This paper provides a comprehensive comparison of a variety of flip-flop designs at subthreshold levels

Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops

Abstract: In this paper, a novel low power flip-flop circuit which is faster than the previous one is proposed. This circuit is applied in two cases, single edge triggered, and double edge triggered. One which works at single edge is called High Speed Modified Hybrid Latch Flip-Flop (HSMHILFF), and another one which works at double edge is called High Speed Double edge triggered Modified Hybrid Latch Flip-Flop (HSDMHILFF). In this proposed design, path between clock and output becomes shorter than the pervious one. This leads to lower delay and power dissipation. HSMHILFF and HSDMHLFF are simulated using HSPICE in 180nm bulk CMOS technology. Compared to the earliest work, the new circuits show better speed and power consumption.

An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems

Abstract: Deeply pipelined systems require flip-flops with low latency and power consumption. Often, the flip-flop must supply both inverted and non-inverted signals to subsequent logic. Generating both outputs at the same time improves performance by equalizing the worst-case delays. In this paper, we present a novel differential flip-flop for deeply pipelined systems. The circuit uses cross-coupled p-transistors as pull-up devices to achieve high energy efficiency. We simulated the design in 90-nm CMOS technology to determine the delay and power consumption. We then repeated the analysis with four other differential flip-flops that produce symmetric outputs. The proposed design achieves the best power-delay product of the five alternatives.

SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof

Abstract: The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.

Low-power/high-performance explicit-pulsed flip-flop using static latch and dynamic pulse generator

Abstract: Latches and flip-flops play important roles in the building of digital CMOS circuits. In the paper, a new low-power positive level-sensitive latch and a simple and innovative dynamic pulse generator are proposed. The pulse generator is then used with the proposed latch to create a low-power and high-performance single edge-triggered flip-flop (SETFF). The proposed positive level-sensitive latch deploys two non-precharge (static) n-stages (SN) in a true-single-phase-clocking (TSPC) scheme. We therefore named our latch SN2. This is because the TSPC latches have the advantage of single clock distribution, less clock routing area, high-speed and no clock skew. Based on the 0.18-μm single-poly six-metal CMOS technology, the SPECTRE simulation results derived for typical input activities showed that the latch can attain a maximum power saving of 29.1% when compared to other reported designs. As for our proposed flip-flop that is derived from the proposed SN2 latch with incorporation of a dynamic pulse generator circuit, it is able to outperform other reported works by about 16.2% to 67.4% for its power-delay product (PDPCQ) that is taken with respect to the clock-to-output delay. The two new designs are therefore suitable for used in low-power and high-performance CMOS VLSI/ULSI applications.

Operation of HTS Toggle-Flip-Flop Circuit With Improved Layout Design

Abstract: Toggle-flip-flop (T-FF) is one of the most important high-Tc superconducting single-flux quantum (HTS SFQ) circuit components and has been designed and fabricated by using YBa2Cu3 O7-delta ramp-edge junction technology. The circuit layout of the T-FF was improved to suppress the junction critical current (Ic) spread in the circuit. Test circuits, which include a T-FF with a single output for evaluating the logic operation and measuring the operating frequency, were fabricated and their operation characteristics were investigated. The T-FF circuit with a single output was successfully operated and finite direct current (dc) supply current margins were obtained at temperatures from 27 to 34 K. Moreover, the maximum operating frequency of the T-FF was estimated to be 360 GHz at 4.2 K and 114 GHz at 41 K. In addition, reduction of dc supply current margins due to thermal noise was also investigated. According to the numerical simulation in which parasitic inductances were taken into account, the narrowest margin in the T-FF circuit wider than plusmn10% was maintained with a bit-error rate (BER) of 10-6 up to 40 K

Boxes: An Engineering Methodology for Calculating Soft Error Rates in SOI Integrated Circuits

Abstract: A simple methodology is necessary to characterize the SEU behavior of large quantities of RAM cell types, latches, flip-flops, other logic cells, I/O cells, etc. Such a methodology, called "Boxes", is being used for the Honeywell S150 radiation-hard 0.15 mum partially-depleted SOI process. Using physics-based equations, this paper shows how to break up each critical transistor into several "boxes", each with its own dimensions and critical charge, for the purpose of calculating soft error rate (SER). The Boxes methodology also allows for calculation of SER due to an ion that must simultaneously strike two separated sensitive volumes in order to cause an upset. This can be the dominant upset mechanism for many types of cells such as certain hardened SRAM's and other cells that obtain radiation hardness via extra transistors (such as triple modular redundancy, the DICE latch, etc.). Boxes also predicts upsets that can occur when an ion strike pulls a circuit node below ground or above the positive power supply. The boxes methodology was applied to a 6 T non-hardened SRAM, a hardened SRAM, and a D-type flip-flop. The theoretical predictions correlated well with experimental vertical ion strike data

Clocked Storage Elements in Digital Systems

Abstract: Clocking is one of the most critical parts of each processor, often determining its performance and largely impacting its power consumption. The clocking subsystem and clocked storage elements in particular are responsible for an increasingly substantial portion of the circuit design improvements needed to accommodate the continuing scaling trends with each processor generation. This chapter describes the conventional clocking strategies and circuit techniques, and reviews the state-of-the art clocked storage elements used in modern microprocessors. In addition, it addresses some emerging methods aimed at handling incoming challenges in the microprocessor design.

State of the art low power (42 mW per flip-flop) 150 GHz+ CML static divider implemented in scaled 0.2 m emitter-width InP DHBTs

Abstract: Recent development efforts in scaling InP DHBT technologies have pushed transistor cutoff frequencies beyond 400 GHz and demonstrated static flip-flop circuits clocking in excess of 150 GHz. Despite the impressive clock rates, obtaining these operating speeds has required an increase in collector current densities that has largely offset the power reductions achieved to date in scaling the emitter area of the devices in these technologies. Further lateral scaling is required to manage thermal concerns and enable logic circuits of greater complexity. Measured results are shown of a static frequency divider realized in a 0.2 m InP/InGaAs/InP DHBT technology that lowers flip-flop power dissipation to 42 mW while clocking at 150 GHz rates. This represents a factor of two improvement in the state of the art power-delay product over previously reported logic circuits operating at >120 GHz clock rates.

Electrical circuit for measuring times and method for measuring times

Abstract: An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.

Radiation hardened latch

Abstract: A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. Therefore, a radiation hardened programmable phase frequency divider that is immune to SEU's is achieved.

Pulsed static flip-flop

Abstract: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

Double-edge Triggered Level Converter Flip-Flop with Feedback

Abstract: In this paper, a double-edge triggered level converter flip-flop (DE-LCFFF) is proposed. The flip-flop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the self-precharging technique to automatically precharge its dynamic node after enough time. An explicit double-edge pulse generator is used to further decrease the power consumption in the proposed LCFF. In addition, the use of pass gate transistors and more simplified structure in the main block of DE_LCFFF leads to a less leakage power consumption. The increase in the speed is achieved by reducing the number of the stack transistors in the discharge path and using less complicated circuit structure. When compared to the previous level converter flip-flops, the proposed LCFF shows considerable reductions in the power consumption, the delay, and the area.