Showing papers on "Flip-flop published in 2007"

Sense amplifier circuit and sense amplifier-based flip-flop having the same

Abstract: A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal. The delay reduction unit is disposed between the input signal applying unit and the ground switch, and reduces a signal delay from when the clock signal to when the evaluation signal pair is output from the second output terminal pair.

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

Abstract: The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

Abstract: In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively

Spin-MTJ based Non-volatile Flip-Flop

Abstract: Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using St microelectronics 90 nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface.

Master-slave flip-flop and clocking scheme

Abstract: A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKin and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKin and a resulting change at the slave latch's output less than it would otherwise be.

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy

Abstract: This paper presents new techniques to evaluate the energy and delay of flip-flop and latch designs and shows that no single existing design performs well across the wide range of operating regimes present in complex systems. We propose the use of a selection of flip-flop and latch designs, each tuned for different activation patterns and speed requirements. We illustrate our technique on a pipelined MIPS processor datapath running SPECint95 benchmarks, where we reduce total flip-flop and latch energy by over 60% without increasing cycle time.

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS

Abstract: This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-VT MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.

Design of Low-Power Double Edge-Triggered Flip-Flop Circuit

Abstract: In this paper, we proposed a double edge-triggered (DET) flip-flop suitable for low-power applications. In addition, the proposed flip-flop can be implemented with fewer transistors than any previous circuit. Simulations have verified the correct operation of the proposed DET flip-flop, for a variety of clock and data rates. Simulation results indicated that the proposed circuit is capable of significant delay and power saving.

Flip-flop circuit

Abstract: To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a master latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

Low-voltage topologies for 40-Gb/s circuits in nanoscale CMOS

Abstract: This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-V T MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.

Flip-flop having logic state retention during a power down mode and method therefor

Abstract: A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.

Master-slave type flip-flop circuit

Abstract: A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit configuring a closed circuit with a first inverter and a second clocked inverter so that an output of the first clocked inverter is input to the first inverter and; the slave latch comprises: a transmission gate to which an output from the first latch circuit is input and a second latch circuit configuring a closed circuit with a second inverter and a third clocked inverter so that an output of the transmission gate is input to the second inverter, respective components configuring the master latch and the slave latch are configured with Sea Of Gate (hereinafter to be referred to as SOG) configuring a gate array, a basic cell of the SOG consists of triplely arrayed N-type transistors and corresponding triplely arrayed P-type transistors, the triplely arrayed N-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size and the triplely arrayed P-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size.

All-Optical Processing Based on a Logic xor Gate and a Flip-Flop Memory for Packet-Switched Networks

Abstract: The routing functionality by all-optically interconnecting semiconductor-based all-optical logic gates and flip-flops is demonstrated in the frame of an all-optical label swapping (AOLS) network. We experimentally show that the output of the all-optical 2-bit correlator is capable of toggling the states of the integrated flip-flop every 2.5 ns via an adaptation stage. High extinction ratios are obtained at the output of the flip-flop, which can be used to feed a high-speed wavelength converter to complete the routing functionality of the AOLS node. The potential integration of these semiconductor optical amplifier integrated Mach-Zehnder interferometer-based devices make the proposed approach a very interesting solution for future packet switched optical networks.

Thermally-induced soft errors in nanoscale CMOS circuits

Abstract: Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation character ized by lower supply voltages VDD and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This paper investigates the noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS flip-flops operated at ultra-low VDD. The theoretical distribution of transition times from one stable operation point to the other stable operation point is also der ived, which is a useful representation of the soft error rate. It is shown that such nanoscale flip-flop designs are extremely sensitive to threshold variations, reducing average failure time to a few days. Monte Carlo simulations are provided to validate the theoretical model and its predictions.

Characterization of a Flip-Flop Metastability Measurement Method

Abstract: We characterize a proposed metastability measurement system in which asynchronous data input and sampling clock frequencies trigger metastability. We develop an equation describing the time interval between data and clock inputs for practical frequencies and show that it takes on discrete values in the absence of jitter and that the presence of jitter perturbs these values. Finally, we present experimental results supporting our characterization

All-Optical Processing Based on a Logic XOR Gate and a Flip-Flop Memory for

Abstract: The routing functionality by all-optically intercon- necting semiconductor-based all-optical logic gates and flip-flops is demonstrated in the frame of an all-optical label swapping (AOLS) network. We experimentally show that the output of the all-optical 2-bit correlator is capable of toggling the states of the integrated flip-flop every 2.5 ns via an adaptation stage. High extinction ratios are obtained at the output of the flip-flop, which can be used to feed a high-speed wavelength converter to com- plete the routing functionality of the AOLS node. The potential integration of these semiconductor optical amplifier integrated Mach-Zehnder interferometer-based devices make the proposed approach a very interesting solution for future packet switched optical networks. Index Terms—Address recognition, all-optical signal processing, Mach-Zehnder interferometer (MZI), optical flip-flop, optical label swapping, packet switching, semiconductor optical amplifier (SOA).

Transparent test method and scan flip-flop

Abstract: Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit

Abstract: In this paper, a novel soft-error-tolerant latch and a novel soft-error-tolerant flip-flop are presented for multiple VDD circuit design. By utilizing local redundancy, the latch and the flip-flop can recover from soft errors caused by cosmic rays and particle strikes. By using output feedback, implicit pulsed clock, and conditional discharged techniques, the proposed flip-flop can behave as a level converter and without the problems of static leakage and redundant switching activity. Since the setup time of the new flip flop is negative, it can further mitigate the impact of single event transient (SET) at the D input of the flip-flop. Experimental results show that compared to the traditional D soft-error-tolerant latch, the delay of the new D latch is 29.1% less but with a more than 16.5% power reduction. Compared to the traditional high speed level converting flip-flop, the D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional one respectively

Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Abstract: A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEL' soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEL soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-mum fully-depleted silicon-on-insnlator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable.

On the Synthesis of Sequential Reversible Circuit

Abstract: Reversible circuits for SR flip flop, JK flip flop, D flip flop, T flip flop, Master Slave D flip flop and Master Slave JK flip flop have been provided with three different logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier proposals for the same. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. It has also been shown that the advantage in gate count obtained in some of the earlier proposals by introduction of New gates is an \textcolor{black}{artifact} and if it is allowed then every circuit block (unless there is a measurement) can be reduced to a single gate. Further, it is shown that a reversible flip flop can be constructed even without a feedback. In this context, some important conceptual issues related to the designing and optimization of sequential reversible circuits have also been addressed.

Scan flip-flop circuit and semiconductor integrated circuit device

Abstract: Disclosed is a scan flip-flop that includes a latch section, a hold section, a first output node and a second output node. The latch section holds data. The hold section captures an inner state, responsive to a control signal, to hold an output state. The first output node outputs a first output signal based on the output state. The second output node outputs a second output signal based on the inner state.

An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop

Abstract: In this paper, we propose a dual-edge triggered and dual-Vth level converting flip-flop (LCFF). The LCFF utilizes many energy-saving features that can be used in a multi-Vdd and multi-Vth system. A novel power-aware latch structure is designed to eliminate the internal power during transition. When operated in sleep mode, the power-aware latch is switch to low-leakage mode and still retain its data. Experimental results show that the proposed LCFF has the lowest PDP among compared FFs.

Scannable flip-flop with non-volatile storage element and method

Abstract: A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

All-optical flip flop based on a symmetric Mach-Zehnder switch with a feedback loop and multiple forward set/reset signals

Abstract: The paper proposed an improved performance for optical flip-flop using symmetric Mach-Zehnder interformeter with a feedback and multiple forward configurations. At the optimum operating condition for the optical flip-flop, high contrast ratio of 22 dB can be achieved. The findings in the paper will have an impact on the design of future optical flip-flop and other optical logic gates such as exclusive OR and NAND gates. A PhD research (Le-Minh) funded by the University Studentship, completed in 2007

A Novel Static Dual Edge-Trigger Flip-flop for High-Frequency Low-Power Application

Abstract: -In this paper, we propose a simple and novel Dual-edge-trigger flip-flop (DETFF). The design has a simple structure which consists of a XNOR pulse generator and a front end sampling circuit. All Simulations were performed at clock frequency of 800 MHz based on Chartered Semiconductor Manufacturing 0.18-mum CMOS technology. Comparison with some of the latest DETFFs shows that the proposed design can achieve the lowest power consumption and Power-delay-product (PDP). In addition, the proposed design has the least number of transistor and is of the least overall silicon area required.

Pulsed state retention power gating flip-flop

Abstract: A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.

A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity

Abstract: A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.

Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection

Abstract: We propose novel compact fault recovering flip-flops (CFR-FFs) which can recover timing error and soft error caused by process variation, supply voltage fluctuation, attacking high energy particle, and so on. Those FFs are composed of an error detector and a clock controller, which re-raises a clock to latch correct data upon error detecting. We propose two kinds of CFR-FFs. One is that the clock rises every cycle, and the other is that the clock rises only when data has changed. These FFs were fabricated by a 0.25 mum CMOS process. Error rates were measured by applying a noise signal to the supply voltage. While the error rate was over 46 % for a conventional FF, it was 1.4 % and 2.2 % for each CFR-FF with only 1.41 and 1.65 times area overhead, respectively.

A Large Scale, Flip-Flop RAM imitating a logic LSI for fast development of process technology

Abstract: We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

Integrated circuit for control of switching power, and switching type power supply

Abstract: PROBLEM TO BE SOLVED: To enable the volume decrease of a power supply itself and the reduction of its cost, by curtailing circuit components. SOLUTION: A current comparator 1 detects the value of a current flowing to a switching element in every switching cycle and controls its ON period by means of a flip flop circuit 2. A leveling circuit 5 converts the peak values of a load current into a time average, and when the comparator 6 detects an overcurrent state from the load current, a latch circuit 8 stops the switching action of the switching element for a certain period. In a delay circuit 7, a delay time from the detection of the overcurrent state of a load to the stoppage of the switching action of the switching element is set. Here, the first reference value (Vth1) of a current comparator 1 is set higher than the second reference value (Vth2) of the comparator 6. COPYRIGHT: (C)2008,JPO&INPIT