Showing papers on "Flip-flop published in 2008"

20 ps Transition Time All-Optical SOA-Based Flip-Flop Used for Photonic 10 Gb/s Switching Operation Without Any Bit Loss

Abstract: A novel scheme for integrable ultrafast all-optical flip- flop is demonstrated. Transition times as low as 20 ps with a contrast ratio higher than 17.5 dB have been experimentally measured. All-optical switching operation in a 2times2 spatial and wavelength preserving switch is reported with a power penalty of about 1 dB. The proposed solution exploits the fast falling edge provided by a semiconductor optical amplifier (SOA) based optical flip-flop. Numerical investigations already demonstrated high extinction ratios (>40 dB) and low switching energies (15.6 fj) for integrated optical flip-flop. On the other hand, slow rising times, due to the cavity length, intrinsically limit such configurations. By using SOA-based logic gates, two flip-flop outputs are combined in a new bistable signal. Both the new rising and falling edges are related to the primary flip-flop falling edge. This way it is possible to eliminate the intrinsic slow rising time that limits the flip-flop configuration based on the coupled ring lasers, without excessively increasing the complexity of the structure and maintaining a reasonably high contrast ratio. Furthermore, the noise on the high level has been improved due to the regenerative properties of the logic gates based on cross-gain modulation and cross-phase modulation in a single nonlinear SOA. Finally, flip-flop output has been used to drive a 2times2 all-optical spatial and wavelength preserving switch based on SOAs. For cross/bar switch configurations, 10 Gb/s error-free operation has been obtained without bit loss.

Timing yield enhancement through soft edge flip-flop based design

Abstract: The first evaluation of a soft-edge flip-flop is presented as an alternative to useful-skew and latch-based designs for variation compensation in a 16-bit 8-tap FIR filter in 0.13 mum CMOS. An 11.2% performance improvement was achieved over a standard hard edge data flip-flop (9.2% when post-silicon useful-skew is applied).

Low-Power Double Edge-Triggered Flip-Flop Circuit Design

Abstract: In this paper, we compare three previously published static double edge-triggered (DET) flip-flops with a proposed design for their transistor counts and power consumptions. The proposed DET flip-flop uses only 12 transistors in addition to the clock driver, and hence requires a small area. Several HSPICE simulations with different input sequences show that the proposed DET flip-flop reduces power consumption up to 85%, as compared to conventional DET flip-flops.

Data retention flip flop for low power applications

Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.

Method and apparatus for mapping flip-flop logic onto shift register logic

Abstract: Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design is identified. The chain of flip-flops includes first and second control signals. A shift register is instantiated in a logical description of the circuit design for the chain of flip-flops. A shift register is instantiated in the logical description for the chain of flip-flops. First and second control chains of flip-flops are instantiated in the logical description for the first and second control signals, respectively. A multiplexer is instantiated in the logical description and is configured to select among an output of the shift register, an asserted logic state, and a de-asserted logic state based on outputs of the first and second control chains.

Robust time borrowing pulse latches

Abstract: Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop Clock trees may be provide with configurable shorting structures that help to reduce clock skew Low-contention clock drivers may drive signals onto the clock tree paths

A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems

Abstract: In this paper, we propose some soft-error-tolerant latches and flip-flops that can be used in dual-VDD systems. By utilizing local redundancy and inner feedback techniques, the latches and flip-flops can recover from soft errors caused by cosmic rays and particle strikes. The proposed flip-flop can be used as a level shifter without the problems of static leakage and redundant switching activity. Implemented in a standard 0.18- mum technology, the proposed latches and flip-flops show superior performance compared to conventional ones in terms of delay and power while keeping the soft-error-tolerant characteristic. Experimental results show that compared to the traditional built-in soft-error-tolerant D latch, the D-QN delay of the new D latch is 29.1% less than that of the traditional built-in soft-error-tolerant D latch while consuming 16.5% less power as well. The D-Q delay and power of the new flip-flop are about 47.7% and 54% less than those of the traditional high speed level-converting flip-flop, respectively. In addition, the proposed flip-flop is more robust to soft errors. The critical charge which represents the minimum charge at the D input required to cause an error of the flip-flop can be increased by more than 46.4%. The time window during which the flip-flop will be erroneous caused by single-event upsets at the D input is reduced by more than 22.2%.

On design of multiple-valued sequential reversible circuits for nanotechnology based systems

Abstract: Multiple-valued reversible logic is an emerging area in reversible and quantum logic circuit synthesis. Multiple-valued reversible logic circuits can potentially reduce the width of the reversible or quantum circuit which is a limitation in current quantum technology. In this paper we propose a method to synthesize the multiple-valued reversible sequential circuits. Implementations for ternary D and T flip flops and edge triggered D flip flop are proposed. Synthesis of generalized fanout circuit and generalized r-valued T flip flop are also presented.

Radiation hardened master-slave flip-flop

Abstract: The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.

An accurate flip-flop selection technique for reducing logic SER

Abstract: The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In particular, the effects of these errors on logic nodes are predicted to play an increasingly large role in determining the overall failure rate of future VLSI chips. While a myriad of techniques have been proposed to mitigate the effects of soft errors, system designers must ensure that the application of these solutions does not come at the expense of other design goals. This work presents a heuristic to selectively apply temporal redundancy to flip-flops within a pipelined logic unit, achieving significant reductions in failures associated with soft errors with minimal overhead.

Delay-Compensation Flip-Flop with In-situ Error Monitoring for Low-Power and Timing-Error-Tolerant Circuit Design

Abstract: With the continuous downscaling of transistors, process variation and power consumption have become major issues. Dynamic voltage and frequency scaling (DVFS) with in-situ timing-error monitoring is an effective method that addresses both issues. However, the conventional implementations of this method, which are mainly based on duplicated circuits, have some implementation-specific constraints. In this paper, the authors propose a delay-compensation flip-flop (DCFF) that does not use duplicated circuit components. It monitors timing errors by directly checking the transient timings of signals. The DCFF adjusts the rising-edge timings of the clock to avoid timing errors and compensates the timing margins between successive stages. Simulations using simulation program with integrated circuit emphasis (SPICE) indicated that the DCFF can operate in a wider supply voltage range than the conventional implementation of DVFS with in-situ timing-error monitoring. A 2.5 ×2.5 mm2 test chip was designed by using a 0.18 µm 5-metal process. An essential circuit component of the DCFF was implemented using semi-custom gate-array chips and its operation was verified. Although more detailed and varied simulations and actual measurements are required as future work, DCFFs can be effectively applied to process-variation tolerance and low-power computation and to optimize the design margin and resolve the false-path problem.

A novel sequential circuit optimization with clock gating logic

Abstract: To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the clock-gating conditions and the next-state function of a Flip-Flop (FF) are correlated and can be used for sequential optimization. We show that the implementation of the next-state function of any FF can be just an inverter if the clock signal is appropriately gated. By exploiting the flexibility between the clock-gating conditions and the next-state function, we propose an iterative optimization technique to minimize the overall timing.

Mtcmos flip-flop with retention function

Abstract: There is provided a MTCMOS flip-flop configured to operate at high speed and to reduce leakage current while realizing a retention function in a sleep mode. The MTCMOS flip-flop may include a signal generator adapted to output an internal clock signal or a sleep mode control signal based on changes in a retention signal and an external clock signal, a master latch adapted to latch an input signal and to output a master latch output signal based on the internal clock signal, and a slave latch connected to an actual ground and adapted to latch the master latch signal, to output a slave latch output signal under control of the internal clock signal, and to maintain the latched signal under control of the sleep mode control signal in the sleep mode.

Semiconductor integrated circuit having active and sleep modes and non-retention flip-flop that is initialized when switching from sleep mode to active mode

Abstract: A semiconductor integrated circuit has an active mode and a sleep mode. The semiconductor integrated circuit is constructed by alternately connecting a plurality of combinational logic circuits and a plurality of flip-flops. The flip-flops include a retention flip-flop that is supplied with electric power and retains the data in the sleep mode, and a non-retention flip-flop that is not supplied with electric power during the sleep mode. The non-retention flip-flop includes an initializing circuit that initializes the non-retention flip-flop when the semiconductor integrated circuit is switched from the sleep mode to the active mode.

Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

Abstract: The low-power/high-speed performance of current-mode logic (CML) D flip-flops based on negative-differential-resistance (NDR) devices is presented. The device count used in the fabricated circuit has been significantly reduced by using the NDR-based D flip-flop topology, leading to enhanced low-power/high-speed performance. The operation of the fabricated NDR-based CML D flip-flop has been confirmed to 36 Gb/s, which is the highest speed among NDR-based differential-mode D flip-flops reported to date. The power consumption of the D flip-flop core circuit was measured to be as low as 20 mW at a power supply voltage of -3.3 V. In addition, a power-delay product of 0.55 pJ has been obtained from the NDR-based CML D flip- flop, which is the lowest value to the authors' knowledge among the previously reported D flip- flops up to operation speeds in the region of 40 Gb/s.

Dual-modulus prescaler circuit operating at a very high frequency

Abstract: The dual-modulus prescaler circuit ( 1 ) is devised to operate at a very high frequency. This circuit includes an assembly formed of two dynamic D-type flip flops ( 12, 13 ), and two NAND logic gates ( 15, 16 ) arranged in negative feedback between the two flip flops. The two flip flops are clocked by an input clock signal (CK) to supply a divided output signal (OUT) whose frequency matches the input clock frequency divided by 2 or by 3 as a function of a division mode selection signal (divb) applied to the input of the first NAND logic gate ( 15 ). One non-inverted output of the second flip flop is connected to one input of the first flip flop ( 12 ). The first dynamic flip flop includes three active branches and supplies a single inverted output signal. A third flip flop ( 14 ) with three active branches receives an inverted mode selection signal (div) at input in order to supply the mode selection signal to the inverted output thereof, clocked by the non-inverted output signal of the second flip flop.

Switching power supply unit

Abstract: PROBLEM TO BE SOLVED: To provide a switching power supply unit where a switching element is stopped and a rise of output voltage is suppressed when a load is light while resistance against noise is improved and an increase of switching loss of the switching element can be suppressed SOLUTION: A control circuit 44 provided with a flip flop 2 holding a state of an output stop signal S5 from an output stop comparator 61, which is input to a D terminal, by one period of a clock signal CLK at every fall timing of the clock signal CLK, which is inputted to a -CK terminal, and a delay circuit 3 delaying fall timing of the clock signal CLK and outputting signals as delay clock signals clk to a NAND circuit 54, and a -R terminal of a flip flop 55 controls on/off of MOSFET 46 of a voltage booster circuit 43 COPYRIGHT: (C)2008,JPO&INPIT

Compound logic flip-flop having a plurality of input stages

Abstract: A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a corresponding input logic function during a first phase of a clock cycle and to store a result of the corresponding input logic function. The flip-flop further includes an output (i.e. ‘slave’) stage coupled to receive the clock signal and the results of the input logic functions from each of the plurality of input stages. The output stage is configured, during a second phase of the clock cycle, to logically combine the results of the input logic functions by performing an output logic function and provide an output signal based on a result of the output logic function.

A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology

Abstract: We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130nm, and 90nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Increased effective flip-flop density in a structured ASIC

Abstract: An H-tree is formed in a conducting layer over a base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of a base array and H-tree. The endpoints of an H-tree can be formed at or near sequential elements. When an H-tree is used as part of a clock structure, clock skew to sequential elements and consumption of routing resources for forming a clock structure can be minimized. When a pulse generator is coupled to an H-tree, at least one flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Double edge triggered flip-flop circuit

Abstract: In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either one of rising edge and falling edge of the clock signal At least one of the first latch circuit and the second latch circuit is configured by an SRAM (Static Random Access Memory) type

Logic and Computer Design in Nanospace

Abstract: Techniques for the advanced logic design of nanodevices and nanolCs in spatial dimensions are being formulated to incorporate specific topologies that satisfy certain requirements of nanotechnology. One of these topologies, the hypercube, is currently being considered for the design of a network-based combinational logic implementation in the form of a hypercube extension called the N-hypercube. We propose the M-hypercube, using a similar topology to design any sequential logic in spatial dimensions. To reduce the complexity of the M-hypercube design, two methods, a top-down and a bottom-up, are presented. The former uses sequential machine decomposition methods and the latter uses a new hypercube topology, called the MN-cell. The MN-cell, consisting of two closely coupled 2D hypercubes, an M-hypercube and an N-hypercube, is a 3D hypercube. It is shown that MN-cells can implement flip-flops and thus can be used as building blocks for sequential logic design in nanodimensions. The logic design of a basic computer in nanospace using MN-cells and N-hypercubes is also presented using several examples.

Soft Error Hardened Latch and Its Estimation Method

Abstract: We propose soft error robust latches which have multi storage nodes and present their efficiencies. The key technology of the latch is a feedback loop circuit with a data node and four gates. We also discuss a method of soft error estimation in robust circuits in this paper. The soft error immunity of this feedback loop circuit is estimated by circuit simulations with two models. The soft error immunity of the latch is estimated by device simulation more accurately. By these precise simulations, the latch is proven to be highly tolerant to soft errors. In addition, the latch protects from not only retention data upset but also transient noise releasing. The latch provides high immunity against all soft error problems with a simple circuit. It is easy to apply the latch technique to various latches, such as single latches, scan latches, and flip-flops.

Semiconductor integrated circuit with flip-flop circuits mounted thereon

Abstract: A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.

IR Drop Reduction via a Flip-Flop Resynthesis Technique

Abstract: Clock skew scheduling for peak current reduction is a conventional technique for solving IR-drop problem in physical design stage. In this paper, we propose two kinds of long delay flip-flops and a heuristic algorithm that is used to resynthesized flip-flops of a circuit. Because the switching times of flip-flops in the resynthesized circuit are staggered, the IR drop effect can be reduced. Unlike clock skew scheduling, our technique not only can be used in physical design stage but also in logic design stage. The other advantages of our technique over the clock skew optimization technique are that our technique has less area overhead and has more opportunities to find a better result.

Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors

Abstract: In this paper, a new technique for implementing low energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch shared (CBS) scheme to reduce the number of clocked transistors in the design. As compared to the other state of the art double-edge triggered flip- flop designs, the newly proposed CBSip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively.

Latch circuit and flip-flop circuit

Abstract: A latch circuit includes: first nodes which are three or more and to which a voltage in a first signal level is set; second nodes which are three or more and to which a voltage in a second signal level obtained by inverting the first signal level is set; and first node voltage control circuits having the first nodes; and second node voltage control circuits having the second nodes. Each of the first node voltage control circuits is connected with at least two of the three or more second nodes, and controls the voltage of the first node based on the voltages of the at least two second modes. Each of the second node voltage control circuits is connected with at least two of the three or more first nodes and controls the voltage of the second node based on the voltages of the at least two first nodes.

Skewed Flip-Flop and Mixed- $V_{t}$ Gates for Minimizing Leakage in Sequential Circuits

Abstract: Mixed V t has been widely used to control leakage without affecting circuit performance. However, existing approaches only target combinational circuits, even though sequential elements such as flip-flops contribute an appreciable proportion of the total leakage. Applying high V t to ordinary flip-flops would reduce the number of combinational gates that can be assigned to high V t, because any timing slacks would be absorbed by the increased setup guard time and propagation delay of the high-V t flip-flops. A skewed flip-flop (SFF) can be constructed by replacing a subset of transistors in a conventional flip-flop with low-leakage devices, such as large- L gate transistors. In terms of leakage and delay, SFFs exhibit very skewed characteristic, which depends on the transistors that are replaced. Our algorithm selectively substitutes SFFs for conventional flip-flops in sequential circuits so as to reduce the leakage while continuing to satisfy the timing constraint. When combined with the mixed-V t combinational circuits, this achieves an average leakage saving of 15% compared to mixed V t alone. The leakage of the flip-flops themselves is cut by 25% on average.

Semiconductor device with speed performance measurement

Abstract: A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.

Flip-flop circuit

Abstract: A pair of transistors receive the input of signals of input data and the inverted input data. An activation circuit, which is provided between the pair of transistors and fixed potential, activates the pair of transistors in a conduction state. A clock control circuit receives a clock signal and sets the activation circuit to a conduction state for a predetermined period starting from an edge timing of the clock signal. The activation circuit includes a first activation transistor and a second activation transistor which are connected in cascade with each other. The clock control circuit turns on both the first activation transistor and the second transistor for the predetermined period starting from the edge timing of the clock signal, and turns off at least one of the first activation transistor and the second activation transistor for a period other than the predetermined period.