Showing papers on "Flip-flop published in 2009"

Design for Low Power and Reliable Flexible Electronics: Self-Tunable Cell-Library Design

Abstract: We propose a self-tunable pseudo-CMOS cell library to address the key challenges of circuit design for flexible electronics. This cell library provides the building blocks for designing complex circuits which are able to operate at a low supply voltage. The circuit reliability is greatly improved by incorporating the post-fabrication tunability into the cells to compensate for the device degradation (e.g., DeltaV TH). Logic gates, such as latches and flip-flops, and larger building blocks, such as shift-registers are, developed to demonstrate the key features and feasibility of this proposed cell library.

Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology

Abstract: Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to single event effects (SEE). The variables characterized included: well structure on the wafer, density of well contacts, logic data pattern, angle of indicence, flip-flop redundancy, variation in sensitive node spacing, and the effect of transients as a function of combinatorial logic type. Analysis of the cross section contribution from the clock, flip-flop and SET target circuitry showed that any hardening technique used in a production integrated circuit may be limited in its effectiveness due to other circuits and logic in the integrated circuit.

An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop

Abstract: In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.

A robust pulsed flip-flop and its use in enhanced scan design

Abstract: Delay faults are frequently encountered in nanometer technologies. Therefore, it is critical to detect these faults during factory test. Testing for a delay fault requires the application of a pair of test vectors in an at-speed manner. To maximize the delay fault detection capability, it is desired that the vectors in this pair are independent. Independent vector pairs cannot always be applied to a circuit implemented with standard scan design approaches. However, this can be achieved by using enhanced scan flip-flops, which store two bits of data. This paper has two contributions. First, we develop a pulsed flip-flop (PFF) design. Second, we present an enhanced scan flipflop design, based on our PFF circuit. We have compared the performance of our pulse based flip-flop with recently published pulse based flip-flop designs, as well as a traditional master-slave D flip-flop. Our PFF shows significant improvements in power and timing compared to the other designs. Our pulse based enhanced scan flip-flop (PESFF) has 13% lower power dissipation and 26% better timing than a conventional D flipflop based enhanced scan flip-flop (DESFF). The layout area of our PESFF is 5.2% smaller than the DESFF. Monte Carlo simulations demonstrate that our design is more robust to process variations than the DESFF.

Non-volatile data-storage latch

Abstract: One embodiments of the present invention is directed to a single-bit memory cell comprising transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA

Abstract: As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, and easily realize the Runtime Reconfiguration (RTR) and multicontext configuration. However, the conventional MRAM technology based on the Field Induced Magnetic Switching (FIMS) writing approach consumes very high power, large circuit surfaces, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM’s further development in memory and logic circuit. Thermally Assisted Switching (TAS)-based MRAM is then evaluated to address these issues. In this article, some design techniques, novel computing architecture, and logic components for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology and a complete TAS-MTJ spice model, some chip characteristic results such as the programming latency (~25ns) and power dissipation (~124pJ) have been calculated or simulated to demonstrate the expected performance of TAS-MRAM-based FPGA logic circuits.

Data latch with structural hold

Abstract: A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.

Low power radio frequency divider

Abstract: In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal. The MMD circuit may also include a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal. The cascade of divide-by-2-or-3 cells and the pulse stretching circuit may be implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits. Each divide-by-2-or-3 cell may be organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop.

Research on metastability based on FPGA

Abstract: Multi-clock is commonly used in complex systems. So if synchronous signals in one clock domain are transferred to another clock domain, they will become asynchronous signals. Asynchronous signals will cause metastable state, which will lead to unpredictable results. How metastabilities led to errors in a system is described first. Then a simulation of RS flip flop using pspice is to show the detail procedure of metastability. To demonstrate how often metastabilities will happen, a FPGA based experimentation is realized by changing the internal layout of flip flop manually, which changes the propagation delay between them.

Supporting scan functions within memories

Abstract: A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch.

Experimental Verification of Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Abstract: Irradiation test results demonstrate the validity of a scan FF technology for separately evaluating SET and SEU soft error rates (SERs) in logic VLSI systems. The SET and SEU soft errors mean the upset caused by latching an SET pulse that originates in combinational logic cell blocks and the upset caused by a direct ion hit to the FF, respectively. A test chip is fabricated using a 0.2-mum fully-depleted silicon-on-insulator standard cell library and irradiated under an LET of 40 MeV-cm2/mg. The SET and SEU soft error rates are successfully measured by the scan FFs on the test chip. A theoretical SET SER estimation from measured SET-pulse widths is also experimentally validated.

Triple latch flip flop system and method

Abstract: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.

A Novel High Performance Scan Architecture with Dmuxed Scan Flip-Flop (DSF) for Low Shift Power Scan Testing

Abstract: Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

An explicit-pulsed double-edge triggered JK flip-flop

Abstract: Pulse-triggered flip-flops are widely used in microprocessors in recent years due to their high performance. JK flip-flops are more powerful than D flip-flops. However, designs of pulse-triggered JK flip-flops are seldom mentioned. Generally, JK flip-flops are designed on the basis of D flip-flops, and have more power consumption and larger delay than D flipflops. An explicit-pulsed double-edge triggered JK flip-flop (ep-DET-JKFF) is proposed, which is designed directly based on the characteristics of JK flip-flops and pulse-triggered flip-flops directly. Simulation using HSPICE and a 0.18µm technology shows that the proposed pulsed JK flip-flop has low power dissipation and small delay comparable to those of published pulsed D flip-flop, and has improvement of 11.4%~32.9% in transistor count, 44.1% in delay and 42.3%~55.9% in PDP (Product of Power and Delay), as compared to the pulsed JK flipflop based on pulsed D flip-flops.

Level shifter flip-flop

Abstract: A flip-flop or other state circuit that includes level-shifting functionality. In connection with a flip-flop, embodiments include an inverter circuit element that has a data input line as its input and a data complement line as its output. The inverter resides in voltage domain that is lower than the voltage domain associated with remainder of the flip-flop.

Low power double-edge triggered flip-flop

Abstract: The invention is related to a low power double-edge triggered flip-flop. The low power double-edge triggered flip-flop of the invention comprises a signal delayed circuit, a XOR circuit and a latch circuit. The low power double-edge triggered flip-flop (DETFF) of the invention is based on using multi-Vth transistors technique. The low threshold voltage transistors are more suitable to drive big loads. By contrast, high threshold voltage transistors are more appropriate to latch data due to their low leakage. Therefore, a single latch double-edge triggered flip-flop utilizing multi-Vth transistors can be a low power and high speed design without paying the price of large area.

Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time

Abstract: A new current-mirror sense-amplifier based Flip-Flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed Flip-Flop at ultra-low voltage (down to 120mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the Pulse Generator stage as well as the delay of the Set-Reset (SR) Latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed Flip-Flop is implemented in a 65nm CMOS technology.

All-Optical counter based on optical flip-flop and optical AND gate

Abstract: An all-optical counter is presented using cascaded stages composed by SOA fiber laser based optical flip-flops and SOA four wave mixing AND logic gates. Two-bit all-optical pulse counting and optical frequency division are demonstrated.

All-optical clocked D type flip-flop exploiting SOA-based optical SR latch and logic gates

Abstract: An integrable all-optical clocked D type flip-flop is demonstrated exploiting SOA-based transparent all-optical SR latch. Nonlinear effects of four wave mixing and cross gain modulation are used for optical logic gate operations.

Low-power dual-edge triggered state retention scan flip-flop

Abstract: This work presents a low-power dual-edge triggered static scanable flip-flop that uses reduced swing-clock and -data to manage dynamic power. The circuit employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining circuit’s state. The static structure of the circuit makes it feasible to be employed in variable frequency power control designs. HSPICE post-layout simulation conducted for 90nm CMOS technology showed that in terms of power-delay product, device count, and leakage power the proposed design is comparable to other high performance static flip-flops.

Towards a balanced ternary FPGA

Abstract: We propose and analyze an organization for a Field-Programmable Gate Array structure that operates using a balanced ternary logic system where the logic set {±1, 0} maps directly to equivalent voltage levels {±1.0V, 0.0V}. Circuits for basic components such as a ternary buffer, flip-flop and LUT are described based on the characteristics of a commercial silicon-on-sapphire process that offers multiple simultaneous transistor thresholds. A simple example of a balanced ternary FIR filter is mapped to the FPGA and some preliminary estimates made of its performance and area.

Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating

Abstract: Dual-edge-triggered flip-flop (DETFF) allows us to use half the clock frequency while maintaining the same throughput, thereby cutting the clock power in half. DETFF-based design, however, requires multiple runs of timing analysis, which is critical for short turn-around time; to make it worse, the number of analysis increases if we use clock gating and multiple clock gating logic, both of which are typical in practical designs. Alternative approach is to perform analysis once assuming the tightest timing condition, which turns out to be too pessimistic. Timing analysis method for DETFF-based circuit with clock gating is proposed for the first time. The method is based on identifying a cluster of nets that have to be associated with multiple required arrival times (RATs); the remaining nets having a single RAT then can be processed by conventional timing analysis. Experiments with several benchmark circuits in 65-nm technology demonstrate that, at 50% point of cumulative slack histogram, the slack from our analysis was 1.78× on average of the slack from conventional timing analysis assuming the tightest timing condition, and 1.30× at 90% point.

Self-synchronising single-stage d flip-flop with high active level of control signal

Abstract: FIELD: computer engineering. ^ SUBSTANCE: invention relates to pulse and computer engineering and can be used in designing self-synchronising flip flops, register and computation devices and digital signal processing systems. The technical outcome of the invention is achieved due to that, in a circuit containing a bistable cell, indicator element, data input, control input, true and complementary outputs and an indicator output, there is also OR-AND-NOT element and an inverter. ^ EFFECT: provision for self-synchronisation of a single-stage D flip-flop with single-phase coding of the data input, with high active level of control signal and paraphrase coding of the data output. ^ 5 cl, 5 dwg

On the trade-off between resolution time and delay times in bistable circuits

Abstract: Flip flops used to store a bit in a register have different requirements to flip flops used in a synchronizer application. The D input must be held stable during the setup and until the Q output appears, these times determine the remaining part of the clock cycle available for computing. On the other hand the D input can violate setup and hold times in a synchronizer, and the reliability of the synchronizer depends on the metastability recovery time constant. We show how these parameters can be traded off in a simple edge triggered D flip flop and other cells.

Apparatus for retention flip-flop

Abstract: A retention flip-flop apparatus is provided to improve the leakage current performance and reduce the power consumption by decreasing the number of cells. The retention flip-flop comprises a master latch, a slave latch(402), a retention latch(404), and two tri-state-inverter(416,426). The master latch delivers the signal of the input terminal to the slave latch according to the control signal. The slave latch outputs the signal delivered from the master latch to the output terminal. The retention latch shares one cell included in the slave latch and stores the output signal of the slave latch. The slave latch and the retention latch shares the tri-state-inverter. The master latch and the slave latch comprise tri-state-inverters(420,436) and one inverter(418,432). The retention latch comprises the tri-state-inverter included in the slave latch and the tri-state-inverter(442) for the retention mode.

Semiconductor integrated circuit including a master-slave flip-flop

Abstract: A semiconductor integrated circuit having a flip-flop with improve soft error resistance, including a controller which controls a clock signal generating circuit to output a first clock signal and a second clock signal with a timing so that logic of data retained in a first data retaining terminal becomes identical to logic of data retained in a third data retaining terminal, and then turns on a first switching circuit to connect between the first data retaining terminal and the first data retaining terminal.

Mtcmos flip-flop with a retention ability

Abstract: A MTCMOS(Multi-Threshold CMOS) flip flop is provided to achieve a high speed operation and a reduction of a leakage current by generating a slip mode control signal and an internal clock signal based on a retention signal and an external clock signal. A MTCMOS(Multi-Threshold CMOS) flip flop comprises a signal generating part(440), a master latch part(400), and a slave latch part(420). The signal generating part outputs an internal clock signal or a slip mode control signal based on a change of a retention signal(RT) and an external clock signal(CLK). The master latch part latches an input signal based on the internal clock signal, and outputs a master latch output signal. The slave latch part latches a master latch signal under a control of the internal clock signal, outputs a slave latch output signal, and maintains a latched signal under a control of a slip mode control signal in a slip mode.

Flip-flop, shift register, and scan test circuit

Abstract: A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.