Showing papers on "Flip-flop published in 2011"

Design of Sequential Elements for Low Power Clocking System

Abstract: Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.

An All-Photonic Molecule-Based D Flip-Flop

Abstract: The photochromic fluorescence switching of a fulgimide derivative was used to implement the first molecule-based D (delay) flip-flop device, which works based on the principles of sequential logic. The device operates exclusively with photonic signals and can be conveniently switched in repeated cycles.

Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems

Abstract: The power-gating (PG) ability of the authors' previously proposed nonvolatile delay flip-flop (NV-DFF) using pseudo-spin-transistors with spin transfer torque magnetic tunnel junctions (STT-MTJs) is computationally analysed. Break-even time (BET) for nonvolatile logic circuits, which is an important index of energy performance for PG systems, is also formulated for the first time. The BET of the proposed NV-DFF can be effectively reduced by the design of the pseudo-spin-transistor parts of the cell. The NV-DFF is applicable to coarse- and fine-grained PG architectures owing to its potential BET of sub-microseconds in practical CMOS logic applications.

Design of MRAM based logic circuits and its applications

Abstract: As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS logic circuits due to the high leakage currents. A number of non-volatile storage technologies such as FRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and their potential applications in the future.

A new architecture for T flip flop using quantum-dot cellular automata

Abstract: QCA is a novel technology which provides implementation of digital circuits in nanoscale. QCA circuits work in higher speed, smaller size and less power consumption compared to conventional CMOS circuits. In this paper, a new design for T flip flop (T-FF), by using of special feature of QCA circuits capabilities, is proposed. This T-FF has additional inputs that can be used better in sequential circuits as memory elements. These inputs can reset and preset T-FF and no more cells needed to add them to the designed circuit. Proposed T-FF is simulated using the QCADesigner and simulation results prove its validity.

Temporal sequential logic hardening by design with a low power delay element

Abstract: A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient (SET) tolerance is demonstrated by simulations using it in a radiation hardened by design (RHBD) master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element incorporates redundancy to mask long transients, which would otherwise limit the circuit hardness. Two FF layouts using the proposed delay element are used in synthesis and auto-place and route experiments to confirm overall power, performance, and density. The first (interleaved) version uses a multi-bit cell interleaving the constituent circuits of four FFs. The second (inline) version interleaves the master and slave circuits to achieve high density while maintaining adequate critical node separation. The latter is shown to be more power efficient and the former is more robust to multiple node collection.

Low Power Efficient D Flip Flop Circuit

Abstract: This paper enumerates low power, high speed design of D flipflop. It presents various techniques to minimize subthershold leakage power as well as the power consumption of the CMOS circuits. The proposed circuit in this paper shows a design for D flip flop to increase the overall speed of the system as compared to other circuits. This technique allows circuit to achieve lowest power consumption with minimum transistor count. General Terms D Flip Flop, Power Delay Product.

Design of a Moore finite state machine using a novel reversible logic gate, decoder and synchronous up-counter

Abstract: Reversible logic is an emerging nanotechnology widely being considered as the potential logic design and implementation of nanotechnology and quantum computing with the main goal of reducing physical entropy gain. Recent advances in reversible logic allow for new avenues in the implementation of reversible combinational circuits. Part of this advancement is the design and implementation of a finite state machine. A proposed novel 4*4 RD gate implemented as a 2-to-4 decoder with low delay and cost is presented, and a novel 4*4 R2D gate used in the implementation of a novel n-to-2n decoder with low cost and delay. A reversible synchronous up-down counter is presented and verified, and a reduced reversible implementation of a JK Flip Flop is implemented in a reduced reversible synchronous up-down counter. This decoder and counter are then utilized in the design of a reversible Moore finite state machine.

Embedded MRAM for high-speed computing

Abstract: As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both the physics and architecture points of view.

Low-power pulse-triggered flip-flop design using gated pull-up control scheme

Abstract: A new implicit type pulse triggered flip–flop design aimed at solving a common transistor stacking problem is presented. A pull-up transistor gating scheme is devised to avoid a bulky discharging path causing excessive power consumption. Via a bootstrap technique, the required gating pulse signal is obtained free from a modified delay inverter design. Circuit analyses and post-layout simulations are provided to prove the superiority of the design in terms of layout area and power–delay product.

Design of a Nanometric Reversible 4-Bit Binary Counter with Parallel Load

Abstract: In recent years, reversible logic has considered as an efficient computing method having its applications in quantum computing, low power computing, nanotechnology and DNA computing. All of the Boolean functions can be implemented using reversible gates. In this paper, we propose a reversible 4-Bit binary counter with parallel load. It has minimum complexity and quantum cost considerably. The proposed circuit is the first attempt of designing a 4-Bit binary counter with parallel load. Counter is essentially a register that goes through a predetermined sequence of states. The reversible gates in the counter are connected in such a way as to produce the prescribed sequence of binary states. This counter receives a 4-Bit data from input and delivers data to D Flip Flop in next cycle. Loading data from input is determined with Load property. The important reversible gates used for our reversible logic synthesis are Feynman gate, Peres gate and Fredkin gate. The proposed circuit becomes a robust design by our optimal method and using these gates. The proposed circuit has minimum number of the garbage outputs and constant inputs in reversible circuit. The proposed circuit is the first attempt and efficient state for a nanometric reversible 4-Bit binary counter. More complex systems could be constructed using the proposed circuit.

Novel CMOS ternary flip-flops using double pass-transistor logic

Abstract: Novel CMOS D-type and modular algebra-based edge-triggered ternary flip-flops using double pass-transistor logic(DPL), are presented. In the proposed circuit scheme, literal functions are also realized by using traditional MOS transistors without any modification of the thresholds. The DPL-based flip-flop has some favourable properties: perfectly symmetrical structure, full logic swing and the maximum possible noise margins, the less complex structure, and no static power consumption. The proposed D-type flip-flop consists of complementary inputs/outputs and is thus a dual rail ternary flip-flop. The modular algebra-based flip-flop can give triple-rail ternary complementary outputs. HSPICE simulations using 0.35µm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design approach.

Flip-flop circuit and scan flip-flop circuit

Abstract: A scan flip-flop circuit includes a pulse generator, a dynamic input unit and a latch output unit The pulse generator generates a pulse signal which is enabled in synchronization with a rising edge of a clock signal in a normal mode, and is selectively enabled in synchronization with the rising edge of the clock signal in response to a logic level of a scan input signal in a scan mode The dynamic input unit precharges a first node to a power supply voltage in a first phase of the clock signal, selectively discharges the first node in the normal mode, and discharges the first node in the scan mode The latch output unit latches an internal signal provided from the first node to provide an output data, and determines whether the output data is toggled based on the clock signal and a previous state of the output data

Dual data rate flip-flop circuit

Abstract: A dual data rate flip-flop circuit for reducing single event upset errors in the flip-flop circuit including two or more latch circuits connected in parallel. The latch circuits each have a clock input, data input, and latch circuit output. The dual data rate flip-flop circuit also includes a C-element, which has a plurality of inputs and a C-element output. The outputs of the latch circuits are provided to inputs of the C-element, and a keeper circuit is connected to the C-element output. An output buffer inverter connects to the C-element output and has an output corresponding to the dual data rate flip-flop circuit output.

Design of low-power quaternary flip-flop based on dynamic source-coupled logic

Abstract: A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18μm CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.

Single-Event Upsets and Distributions in Radiation-Hardened CMOS Flip-Flop Logic Chains

Abstract: Single-event upsets are studied in digital logic cells in a radiation-hardened CMOS SOI technology. The sensitivity of SEU to different strike locations and hardening approaches is explored using broadbeam and focused beam experiments. Error distributions in chains of logic flip-flops are studied to determine the impact of various cell designs and hardening techniques on upset uniformity.

Investigation of multi cell upset in sequential logic and validity of redundancy technique

Abstract: Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.

Semi-dynamic flip-flop with partially floating evaluation window

Abstract: Implementations of the present disclosure involve a semi-dynamic flip-flop circuit incorporating a partially floating evaluation window that provides a faster data to output delay, a PMOS keeper device may be placed in series with an existing keeper circuit of the semi-dynamic flip-flop circuit. The gate of the PMOS series keeper device may be connected to a shut-off signal of the semi-dynamic flip-flop circuit that provides a three gate delay, self-timed positive pulse to control the keeper circuit. The PMOS series keeper device effectively turns off the keeper circuit when the clock signal rises but turns in back on after a three gate delay to sustain the precharge state of the dynamic node. The effective turning on and off of the keeper circuit portion may decrease the data to output delay of the flip-flop, resulting in higher performing microprocessors.

Scan flip-flop circuit having fast setup time

Abstract: A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.

Ultra compact non-volatile flip-flop for low power digital circuits based on hybrid CMOS/magnetic technology

Abstract: Complex systems are mainly integrated in CMOS technology, facing issues in advanced process nodes, in particular for power consumption and heat dissipation. Magnetic devices such as Magnetic Tunnel Junction (MTJ) have specific features: non-volatility, high cyclability (over 1016) and immunity to radiations. Combined with CMOS devices they offer specific and new features to designs. Indeed, the emerging hybrid CMOS/Magnetic process allows integrating magnetic devices within digital circuits, modifying the current architectures, in order to contribute to solve the CMOS process issues. We present a high performance innovative non-volatile latch integrated into a flipflop which can operate at high speed. It can be used to design non-volatile logic circuits with ultra low-power consumption and new functionalities such as instant startup. This new flip-flop is integrated as a standard cell in a full Magnetic Process Design Kit (MPDK) allowing full custom and digital design of hybrid CMOS/Magnetic circuits using standard design tools.

Adiabatic Two-Phase CPAL Flip-Flops Operating on Near-Threshold and Super-Threshold Regions

Abstract: Low-power adiabatic flip-flops operating on near-threshold and super-threshold regions are investigated in this paper. The flip- flops are realized using two-phase CPAL (complementary pass-transistor adiabatic logic) circuits. A traffic light controller operating on near-threshold and super- threshold regions is verified. All circuits are simulated using NCSU PDK 45 nm technology by varying supply voltage from 0.4 V to 0.9 V with 0.1 V steps. Based on the HSPICE simulation results, the energy consumption of the medium-voltage adiabatic flip-flops using two-phase CPAL circuits can be greatly reduced with reasonable speed.

Flip-flop for low swing clock signal

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Abstract: Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.

Flip-flop including keeper circuit

Abstract: A flip-flop includes a transmission circuit configured to transmit data to a transmission line in response to a clock signal and a complementary clock signal. The flip-flop further includes a keeper circuit configured to latch data of the transmission line in response to the clock signal and the complementary clock signal to maintain the data of the transmission line constant.

Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit

Abstract: The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.

Comparative analysis of flip-flop designs for soft errors at advanced technology nodes

Abstract: For advanced fabrication technology nodes, novel single-event related failures are being observed. This paper details efforts to use 3D TCAD simulations to model these failure mechanisms and develop mitigation techniques for flip-flop designs. Simulation, as well as experimental, results are used to show validity of such an approach for future CMOS technologies.

Flip-flop circuit with multiple configurations

Abstract: The invention belongs to the sequential circuit technical field, in particular to a flip-flop circuit which can be multiply configured. The circuit is formed by connecting a data input control circuit, a synchronous reset control circuit, a clock control circuit and a flip-flop main circuit. The invention can be configured into a rising edge or trailing edge flip-flop circuit, a synchronous or asynchronous flip-flop circuit, all the 28 types of D flip-flop circuits with set terminals, clear terminals and enables, and latch circuits for users selecting.

Novel Nanowire-Based Flip-Flop Circuit Utilizing Gate-Controlled GaAs Three-Branch Nanowire Junctions

Abstract: A novel set-reset flip-flop (SR-FF) circuit integrating gate-controlled GaAs three-branch nanowire junctions (TBJs) is designed, fabricated, and characterized Fundamental logic gates including AND, NOT, and NAND are constructed using Schottky wrap gate (WPG)-controlled TBJs together with inverter circuits that have the same configuration The present SR-FF circuit is simply designed using a pair of cross-coupled TBJ-based NAND gates The circuit is successfully fabricated on a GaAs-based hexagonal nanowire network Its correct operation with a voltage transfer gain larger than unity is demonstrated Reduction of circuit area and possible operation speed are also discussed

High density flip-flop with asynchronous reset

Abstract: A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.