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Showing papers on "Flip-flop published in 2015"


Journal ArticleDOI
TL;DR: In this article, the design of control circuit for a solar fed cascaded multilevel inverter to reduce the number of semiconductor switches is presented in order to reduce harmonic distortion by increasing the levels.
Abstract: The design of control circuit for a solar fed cascaded multilevel inverter to reduce the number of semiconductor switches is presented in this study The design includes `binary', `trinary' and `modified multilevel connection' (MMC)-based topologies suitable for varying input sources from solar photovoltaic's (PV) In binary mode, 2 Ns+1 - 1 output voltage levels are obtained where N s is the number of individual inverters This is achieved by digital logic functions which includes counters, flip-flops and logic gates In trinary mode, 3 Ns levels are achieved by corresponding look-up table MMC intends design in both control and power circuits to provide corresponding output voltage levels by appropriate switching sequences Hence to obtain a 15-level inverter, the conventional method requires 28 switches and in binary mode 12 switches are needed In trinary mode with the same 12 switches, 27 levels can be obtained whereas in MMC only 7 switches are employed to achieve 15 levels The advantage of these three designs is in the reduction of total harmonic distortion by increasing the levels Simulations are carried out in MATLAB/Simulink and comparisons were made All the three topologies are experimentally investigated for a 3 kWp solar PV plant and power quality indices were measured

81 citations


Journal ArticleDOI
TL;DR: In this article, a novel all optical SR flip-flop memory based on two optical NOR gates using 2D photonic crystals (PhC) is presented, which is based on four nonlinear photonic crystal ring resonator and T-type waveguide.
Abstract: The photonic crystals (PhC) draw significant attention to build all optical logic devices and considered one of the solutions for the opto-electronic bottleneck via speed and size. The paper presents a novel all optical SR flip flop memory based on two optical NOR gates using 2D PhC. The design of optical Flip Flop is based on four nonlinear photonic crystal ring resonator and T-type waveguide. The total size of the proposed optical memory flip flop is equal to 30 μm × 30 μm. The structure has lattice constant ‘a’ is equal to 630 nm and bandgap range from 0.32 to 044. The flip flop design has a switching time in few Picoseconds and low power input of 50 mW. The PhC structure has a square lattice of silicon rod with refractive index of 3.39 in air. The overall design and the results are discussed through the experimental implementation and the numerically simulation to confirm its operation and feasibility.

47 citations


Journal ArticleDOI
TL;DR: This paper constitutes the mathematical description of the proposed device and thereafter compilation using MATLAB, and is carried out by simulating the proposeddevice with the beam propagation method.
Abstract: Electrical component speed is a major constraint in high-speed communications. To overcome this constraint, electrical components are now being replaced by optical components. The application of optical switching phenomena has been used to construct the design of the D flip-flop and T flip-flop based on the electro-optic effect in a Mach-Zehnder interferometer (MZI). The MZI structures show the powerful ability to switch the optical signal from one output port to the other. Hence, it is possible to construct some complex optical combinational digital circuits using the electro-optic-effect-based MZI structure as a basic building block. This paper constitutes the mathematical description of the proposed device and thereafter compilation using MATLAB. The study is carried out by simulating the proposed device with the beam propagation method.

40 citations


Journal ArticleDOI
TL;DR: The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops and uses a small number of the pulsed clock signals instead of the conventional single pulsing clock signal.
Abstract: This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 $\mu{\rm m}$ CMOS process with ${\rm V}_{\rm DD}=1.8{\rm V}$ . The core area is $6600\ \mu{\rm m}^{2}$ . The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops.

39 citations


Journal ArticleDOI
TL;DR: A data-dependent power gating technique is proposed to mitigate the high static current during retention and back-to-back writing of the identical input data and achieves several orders of magnitude energy saving at the expense of 1.56X area compared to a standard enhanced scan flip-flop.
Abstract: We present two non-volatile flip-flops (NVFFs) that incorporate magnetic tunnel junctions (MTJ) to ensure fast data storage and restoration from intentional and unintentional power outages. The proposed designs also facilitate enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The proposed NVFF eliminates additional write drivers, and can operate at up to 2 GHz at 1.1 V, with 0.55 pJ of energy consumption in 22 nm predictive technology. We also address the issue of write asymmetry of MTJ through careful transistor upsizing to achieve near uniform write latency. A data-dependent power gating technique is proposed to mitigate the high static current during retention and back-to-back writing of the identical input data. The proposed gated NVFF achieves several orders of magnitude energy saving at the expense of 1.56X area compared to a standard enhanced scan flip-flop.

26 citations


Journal ArticleDOI
TL;DR: A novel placement flow with clock-tree aware flip-flop (FF) merging and MBFF generation is introduced, and the corresponding algorithms to simultaneously minimize FF power and clock latency when applying MBFFs during placement are proposed.
Abstract: Utilizing multibit flip-flops (MBFFs) is one of the most effective power optimization techniques in modern nanometer integrated circuit design. Most of the previous works apply MBFFs without doing placement refinement of combinational logic cells. Such problem formulation may result in less power reduction due to tight timing constraints with fixed combinational logic cells. This paper introduces a novel placement flow with clock-tree aware flip-flop (FF) merging and MBFF generation, and proposes the corresponding algorithms to simultaneously minimize FF power and clock latency when applying MBFFs during placement. Experimental results based on the IWLS-2005 benchmark show that our approach is very effective in not only FF power but also clock latency minimization without degrading circuit performance. To our best knowledge, this is also the first work in the literature which considers clock trees when generating MBFFs during placement.

25 citations


Journal ArticleDOI
TL;DR: In this paper, a low-power sense-amplifier-based flip-flop (FF) is presented, using a simplified single-ended pass transistor-based latch design.
Abstract: A novel low-power sense-amplifier-based flip-flop (FF) is presented. Using a simplified single-ended pass transistor-based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense-amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive post-layout simulations.

20 citations


Journal ArticleDOI
TL;DR: In this article, a bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V−1 s−1 in the saturation region and a threshold voltage (VTH) of −2.4 V in ambient air operation conditions.
Abstract: Organic reset–set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V−1 s−1 in the saturation region and a threshold voltage (VTH) of −2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

17 citations


Proceedings ArticleDOI
24 May 2015
TL;DR: Novel pulse-clocked latch based flip-flops that mitigate not just single event upsets but also single event transients that are an increasing threat in high performance logic.
Abstract: Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.

14 citations


Proceedings ArticleDOI
12 Oct 2015
TL;DR: The design of a CMOS 40 nm D Flip-Flop cell is presented and the laser fault sensitivity mapping both with experiments and simulation results and an upgrade of the simulation model used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology.
Abstract: This paper presents the design of a CMOS 40 nm D Flip-Flop cell and reports the laser fault sensitivity mapping both with experiments and simulation results. Theses studies are driven by the need to propose a simulation methodology based on laser/silicon interactions with a complex integrated circuit. In the security field, it is therefore mandatory to understand the behavior of sensitive devices like D Flip-Flops to laser stimulation. In previous works, Roscian et al., Sarafianos et al., Lacruche et al. or Courbon et al. studied the relations between the layout of cells, its different laser-sensitive areas and their associated fault model using laser pulse duration in the nanosecond range. In this paper, we report similar experiments carried out using a shorter laser pulse duration (30 ps instead of 50 ns). We also propose an upgrade of the simulation model they used to take into account laser pulse durations in the picosecond range on a logic gate composed of a large number of transistors for a recent CMOS technology (40 nm).

14 citations


Journal ArticleDOI
TL;DR: In this article, a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets is presented, which is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flipflops.
Abstract: In modern scaled process technologies a single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate. Consequently, hardening flip-flops to transients at the data and control inputs, as well as to single event upsets, due to either single or multi-node upsets is increasingly important. This paper presents a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets. The methodology is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flip-flops. Comparison of the hardness, as measured by estimated upset cross-section, is also facilitated. The results also show the importance of specific circuit design aspects to achieving hardness. One of the comparisons to prior designs includes a comparison of the cross-section as determined by the proposed circuit simulation methodology to ion beam results.

Proceedings ArticleDOI
19 Mar 2015
TL;DR: This brief proposes the binary up counter using T flip flop, designed and the functionality of the counter circuit was verified using QCADesigner tool.
Abstract: As CMOS technology has a scaling limitation in deep nanometer technologies, the best alternative for CMOS technology is a Quantum - Dot Cellular Automata (QCA) technology. Quantum dot Cellular Automata has the combined nature of both quantum mechanics and cellular automata. The QCA technology has many advantages than transistor based technology such as small size, high speed, and low power consumption. The working principle of QCA technology is at the molecular level. In conventional CMOS technology, transistors are used to create a logic gate. But in QCA technology, QCA cells are used to create logic gates and wire. The basic logic elements are an inverter and the majority gate. By using these elements many of the combinational and sequential circuits are created. In this brief, we propose the binary up counter using T flip flop. 2 bit and 3 bit Counters are implemented using the above mentioned QCA technology. The layout was designed and the functionality of the counter circuit was verified using QCADesigner tool.

Journal ArticleDOI
TL;DR: The proposed sense amplifier- based design is more compact than previously reported master-slave latch based nonvolatile designs and presents a modified data restore circuit for more robust read operation at subthreshold voltage supply levels.
Abstract: In this work, a zero-leakage nonvolatile flip-flop architecture based on a differential CMOS sense-amplifier flip-flop is presented. The flip-flop stores data in complimentarily programmed resistive memory devices during inactive period while power supply is turned off and then restores the data to flip-flop outputs once power supply is turned back on. The resistive memory technology considered here are known as programmable metallization cell (PMC) that switches via metal ion transport within a solid electrolyte. Simulations of the proposed circuit using a PMC compact model fitted to experimental data are performed to estimate the reliability of the read operation and energy consumption for both nominal and sub-threshold power supply regimes. Energy and reliability tradeoffs in the choice of the programmable low resistance state are also discussed. The proposed sense amplifier- based design is more compact than previously reported master-slave latch based nonvolatile designs and presents a modified data restore circuit for more robust read operation at subthreshold voltage supply levels. The wide margin between high and low resistance states of the PMC devices further improves robustness of the flip-flop. Lastly, possible extension of this architecture for low power logic computation application is briefly discussed.

Journal ArticleDOI
TL;DR: In this paper, a new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented, which consumes much lower power and can operate normally in the ultra wide voltage range.
Abstract: A new boost bulk-driven sense-amplifier-based flip-flop (BBDSAFF) is presented. First, thanks to the boost and bulk-driven technique, the BBDSAFF consumes much lower power and can operate normally in the ultra-wide voltage range. Secondly, the adopted pseudo-PMOS dynamic technique in the RS latch output stage can greatly reduce the delay and improve the driving capability. The simulation results show advantages of high-speed, low power dissipation and very small and symmetrical rise/fall delay. Under the same simulation conditions, power dissipation, delay and PDP of the Strollo sense-amplifier-based flip-flop is 31 μW, 107 ps and 3.32 fJ whereas that of the proposed bulk-driven SAFF is 29 μW, 94 ps and 2.73 fJ. This low power consumption and high-speed BBDSAFF can be applied in various fields, such as ultra-dynamic voltage scaling VLSI, circuits, low power dissipation counter-clock systems and microprocessors.

Patent
06 Jul 2015
TL;DR: A flip-flop circuit includes a master latch, a slave latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling as discussed by the authors.
Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

Patent
19 Feb 2015
TL;DR: In this article, a flip-flop consisting of a master latch, a slave latch, and a multiplexer is presented, where the master latch has an input for receiving a data input signal and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal.
Abstract: In one form, a flip-flop comprises a master latch, a slave latch, and a multiplexer. The master latch has an input for receiving a data input signal, and an output, and operates in transparent and latching modes during respective first and second phases of a clock signal. The slave latch has an input coupled to the output of the master latch, and an output, and operates in the transparent and latching modes during the second and first phases of the clock signal, respectively. The multiplexer has a first input coupled to the output of the slave latch, a second input coupled to the output of the master latch, and an output for providing a data output signal, and provides the first input to the output during the first phase of the clock signal, and the second input to the output during the second phase of the clock signal.

Patent
09 Feb 2015
TL;DR: In this article, a D-type flip-flop with a slave latch is presented, where the transmission element fetches an output of a first latch circuit and outputs the fetched output to a first node based on a clock signal.
Abstract: A D-type flip-flop according to embodiments comprises: a transmission element configured in a slave latch, the transmission element fetching an output of a first latch circuit and outputting the fetched output to a first node, based on a clock signal; a first latch circuit constituting element configured in the first latch circuit, the first latch circuit giving an output of one logical value to the first node through the transmission element with the output fixed in a second mode; and a second latch circuit constituting element configured in the second latch circuit that holds a signal which appears at the first node, the second latch circuit constituting element giving an output of other logical value to the first node based on the clock signal with the output fixed in the second mode.

Patent
Ilyas Elkin1, Ge Yang1
27 May 2015
TL;DR: In this article, a flip-flop circuit may include a master latch and a slave latch, and the slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa.
Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Patent
09 Mar 2015
TL;DR: In this paper, a process utilized in an integrated circuit design methodology may be used to assess and organize individual bits within multi-bit clocked storage devices (e.g., flip-flops) for use in the Integrated circuit design.
Abstract: A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.

Proceedings ArticleDOI
22 Nov 2015
TL;DR: A new transistor level scan cell design is proposed to eliminate the scan multiplexer off the functional path and thus in improving the timing performance of integrated circuits.
Abstract: The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.

Proceedings ArticleDOI
17 Jun 2015
TL;DR: A 0.4-1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency.
Abstract: A 0.4–1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency. The inherent firstorder noise-shaping property allows the proposed frequency subtraction circuit to mitigate spur-noise issues found in conventional digital BBPLLs. The fabricated BBPLL including a 10bit ring-DCO circuit has an in-band phase noise of −97dBc/Hz at 100kHz and an integrated RMS jitter (from 20kHz to 2MHz) of 2.8ps while consuming 2.7mW at 1.6GHz and occupying 0.019mm2. The PLL circuit has an FoM of −226.7dB.

Proceedings ArticleDOI
15 May 2015
TL;DR: Low Power Conditional Pulse Control with Transmission Gate Flip-Flop (CPCTG-FF) design based on signal feed through scheme is proposed, which removes the long discharging path problem with intermediate nodes using the pulse generation control logic with transmission gate.
Abstract: In the present work, Low Power Conditional Pulse Control with Transmission Gate Flip-Flop (CPCTG-FF) design based on signal feed through scheme is proposed. The proposed design removes the long discharging path problem with intermediate nodes using the pulse generation control logic with transmission gate (which facilitates a faster discharge operation). Transmission gate and a NMOS are used to control the input data and clock circuit to reduce the power dissipation along the critical path. As a result, very low power dissipation occurs when there is no switching. T-Spice (Tanner 14.1) is used for the simulation purposes. All simulation results are based on using CMOS 90-nm technology at 500MHz clock frequency. Its maximum power saving compared to conditional pulse enhancement scheme flip-flop [1] is up to 16.84% and compared to signal feed through scheme designs [2] is up to 37.19%.

Proceedings ArticleDOI
01 Sep 2015
TL;DR: An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both SEU and SET with reduced power consumption and reduces energy per operation by 18% over an improved version of the prior approach.
Abstract: An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both SEU and SET with reduced power consumption. The approach utilizes commercial CAD tools. An advanced encryption system is implemented with the proposed design is compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation by 18% over an improved version of the prior approach, with negligible area impact.

Patent
22 Jul 2015
TL;DR: The flip-flop circuit as discussed by the authors comprises a master latch and a secondary latch driven by clocking signals with same phases, and it is low in dynamic power consumption compared to the flip-flat circuit.
Abstract: The invention provides a flip-flop circuit, and belongs to the technical field of semiconductor integrated circuits The flip-flop circuit comprises a master latch and a secondary latch driven by clocking signals with same phases; the master latch comprises a first logic module for selectively and at least performing AND logic processing on an input data signal and the clock signal, a second logic module for at least performing NOR logic processing on the clock signal and an output signal of a third logic module, and the third logic module for selectively and at least performing the NOR logic processing on the output signal of the first logic module and the output signal of the second logic module so as to output a result to the second logic module; the secondary latch comprises a fourth logic module for at least performing the NOR logic processing on the output signal of the second logic module and the output signal of a fifth logic module, and the fifth logic module for at least performing the AND logic processing on the clock signal and an inversion signal of the output signal of the fourth logic module The flip-flop circuit is low in dynamic power consumption

Patent
05 Aug 2015
TL;DR: In this article, a delay flip-flop consisting of a clock module, delay filtering module, a master-slave DICE latch module and an output module is used for correcting inner node upset caused by the single-particle effect.
Abstract: A delay flip-flop comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module outputs a corresponding data signal to the data output module according to a clock signal that is output from the clock module and an outer data signal that is received through the delay filtering module. The master-slave DICE latch module is composed of a master-grade module and a slave-grade module. The delay filtering module is used for preventing entering of a transient pulse which is caused by a single event effect into the register. The master-slave DICE latch module is used for correcting inner node upset which is caused by the single-particle effect. The delay filtering module performs a function of preventing a single event transient pulse. The master-slave DICE latch module prevents overturning of an inner storage node, thereby performing a function of preventing single event upset. A protective belt structure is added in layout design. The structure of the delay flip-flop effectively restrains single event latchup, and facilitates reduction of a single event transient pulse width in a circuit.

Journal ArticleDOI
TL;DR: The proposed Embedded Logic Flip-flop (ELFF) will reduce the implementation area, power dissipation and delay, and has 20% better performance compared to the existing Dual Dynamic Node Flip- flop-Embedded Logic Module (DDFF-ELM).

26 Oct 2015
TL;DR: A low power flip flop design featuring pulse triggered structure based on signal feed-through scheme is presented which successfully solves the long discharging path problem in a various pulse triggered flip Flop design and achieve a better power performance and better speed.
Abstract: Flip-flops and latches are the most important elements of a design for both a delay and energy point of view. In many electronics design low power consumption is basic need in most of the applications. The energy performance requirements enhance the most designers of next generation system towards the least possible power consumption. The power consumption is basically reduced by scaling of a power supply voltage.Flip flops typically consumes more than 50% of random logic power in the SoC chip, because of redundant transition of internal node. A low power flip flop design featuring pulse triggered structure based on signal feed-through scheme is presented which successfully solves the long discharging path problem in a various pulse triggered flip flop design and achieve a better power performance and better speed. In this paper we have studied all the major techniques to achieve a low power flip flop and presented their comparison.

Proceedings ArticleDOI
23 Nov 2015
TL;DR: An 8-bit shift register is designed by using D-Flip flop that the existing connections are performed through the second layer and by the second type of metal and its area and power has been calculated and also the simulation results have been shown.
Abstract: n this paper an 8-bit shift register is designed by using D-Flip flop that the existing connections are performed through the second layer and by the second type of metal and its area and power has been calculated and also the simulation results have been shown. The obtained results indicate that the performance of this shift register compared with the other shift registers which are built in the other way is more desirable and better. The closed circuit layout related to these shift registers is shown as well.

Patent
22 Jul 2015
TL;DR: In this article, a piece of metastable state reducing D flip-flop equipment comprising a flipflop body which is provided with a signal input port is characterized, where the signal input ports is connected with a phase inverter, and the output end of the phase inverters is connected by a differential assembly.
Abstract: The invention relates to a piece of metastable state reducing D flip-flop equipment comprising a flip-flop body which is provided with a signal input port. The metastable state reducing D flip-flop equipment is characterized in that the signal input port is connected with a phase inverter, and the output end of the phase inverter is connected with a differential assembly. Meanwhile, the differential assembly is provided with an output port, the differential assembly is composed of at least two identical latches (a master latch and a slave latch) which are connected, and the phase inverter converts a secondary differential output signal into single-end output. Therefore, the occupied area is reduced, and the overall stability of operation is improved. Moreover, there is no need to add an additional feedback branch and external voltage bias for different processes, and the equipment can be conveniently used in various processes through appropriate design.

Journal ArticleDOI
P. Umarani1
TL;DR: A new GDI T-Flip flop is designed, which has less number of transistors than other G DI T-flip flops and also, it consumes low power and lesser delay and a high performance Asynchronous down counter is developed in this paper.
Abstract: As the technology is increasing day by day in electronic industry, it needs a field which involves packing more and more devices into smaller area. Along with Very Large Scale Integration (VLSI) is a process of integrating much number of devices into a single chip. According to Moore's law the competence of an IC has increased in terms of power, speed and area. Hence the GDI technique is used here, in which many complex logic functions can be designed by using only two transistors. Along side, the memory device plays an important role in digital systems, where the flip flops are the basic building blocks of digital electronic systems. Asynchronous logic in digital system does not use common clock pulse, in place the precious state output will be considered as clock pulse to the next state. Based on the concept of T-flip flop, a new GDI T-Flip flop is designed, which has less number of transistors than other GDI T-flip flops and also, it consumes low power and lesser delay. With this energy efficient GDI T-Flip flop, a high performance Asynchronous down counter is developed in this paper. The comparison is done on the basis of four performance parameters i.e. total Area, delay, Power consumption and power-delay product.