Showing papers on "Flip-flop published in 2016"
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TL;DR: A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article, which has features of high performance and low power.
Abstract: The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 µm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.
13 citations
12 Feb 2016
TL;DR: In this article, the authors proposed a novel CPSFF using Multi-Threshold voltage CMOS (MTCMOS) technique which reduces the power consumption by approximately 20% to 70% than the original CPSFF and double edge triggering and low swing clocking can be easily incorporated into the new flip-flop.
Abstract: Power consumption plays an important role in any integrated circuit and is listed as one of the top three challenges in International technology roadmap for semiconductors. In any integrated circuit, clock distribution network and flip -flop consumes large amount of power as they make maximum number of internal transitions. In this paper, various techniques for implementing flip–flops with low power clocking system are analyzed. Among those techniques clocked pair shared flip-flop (CPSFF) consume least power than conditional data mapping flip flop (CDMFF), conditional discharge flip flop (CDFF) and conventional double edge triggered flip-flop(DEFF). We propose a novel CPSFF using Multi-Threshold voltage CMOS (MTCMOS) technique which reduces the power consumption by approximately 20% to 70% than the original CPSFF. In addition, to build a clocking system, double edge triggering and low swing clocking can be easily incorporated into the new flip-flop.
12 citations
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01 Sep 2016TL;DR: This T flip-flop is employed in designing an Up-Down counter, based on the implication operations using memristors, which will occupy lesser area as compared to its conventional CMOS-based design.
Abstract: ‘Memristor’ is a new emerging nanodevice that is gaining a lot of appreciation from the researchers these days. They possess dual properties of resistor, memory and find immense application in the fields of nanoelectronic circuit and memory designs. Material implication logic is applied in memristor-based circuit designs as it can be performed easily using two memristors and one resistor. In this paper a memristor-based T (toggle) flip-flop is implemented using material implication logic. Thereby this T flip-flop is employed in designing an Up-Down counter, based on the implication operations using memristors. The designs thus presented for the T flip-flop and counter need 6, 16 memristors respectively. Memristor technology being highly dense, our counter design will occupy lesser area as compared to its conventional CMOS-based design. Also the proposed T flip flop takes 11 computation steps to generate its outputs and 52 steps are needed by the Up-Down counter to perform its operation. Moreover in our memristor-based counter circuit, counting can be started, stopped and resumed at any desired logic states by simply controlling the externally applied voltages.
11 citations
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01 Sep 2016TL;DR: In this paper, the authors proposed a non-redundant flip-flop with stacked transistors based on Adaptive Coupling Flip-Flop (ACFF) with lower power consumption in a 65 nm Fully Depleted Silicon On Insulator (FDSOI) process.
Abstract: We propose a non-redundant Flip-Flop (FF) with stacked transistors based on Adaptive Coupling Flip-Flop (ACFF) with lower power consumption in a 65 nm Fully Depleted Silicon On Insulator (FDSOI) process. The slave latch in ACFF is much weaker against soft errors than the master latch. We design several FFs with stacked transistors in the master or slave latches. We investigate radiation hardness of the proposed FFs by α particle and neutron irradiation test. The proposed FFs have higher radiation hardness than conventional DFF. There is no error in the proposed AC slave stacked FF which has stacked transistors only in the slave latch by α particle and neutron irradiation test. It can decrease soft error rates despite the performance equivalent to that of ACFF.
9 citations
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TL;DR: By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types.
Abstract: D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study. The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.
7 citations
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01 Dec 2016TL;DR: A radiation-hardened flip-flop immune to the Single Event Upset (SEU) effect was achieved through the use of C-elements and redundant storage elements and was implemented using 48 transistors and occupied an area of 30.78 um2.
Abstract: We propose a radiation-hardened flip-flop immune to the Single Event Upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. We take advantage of the property of C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the Flip-Flop. The Flip-Flop was implemented using 48 transistors and occupied an area of 30.78 um2, using 65nm CMOS process. It consumed 22.6% less transistors as compared to the traditional SEU resilient TMR Flip-flop.
7 citations
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18 May 2016TL;DR: Simulation results show that the proposed flipflops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops.
Abstract: In this paper, two timing error masking flip-flops have been proposed, which are immune to metastability. The proposed flip-flops exploit the concept of either delayed data or pulse based approach to detect timing errors. The timing violations are masked by passing direct data instead of master latch output to slave latch. Simulation results show that the proposed flip-flops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops [14]. The proposed flip-flops can be used in dynamic voltage and frequency scaling (DVFS) applications. A 16-bit adder is implemented to evaluate the functionality of the proposed flip-flops in DVFS frame work and the simulation results show that the adder using the proposed flip-flop can reduce up to 48% power consumption or improve the performance up to 50% in typical process corners compared to conventional worst case design.
7 citations
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27 Jun 2016TL;DR: In this article, a comprehensive study for IECRL, PFAL and EACRL 4-phase quasi-adiabatic logic families has been done and a new resettable quasi-adabatic flip-flop circuit is proposed for each of them.
Abstract: Resettable adiabatic flip-flops are essential in the design of adiabatic counters, thus, a comprehensive study for IECRL, PFAL and EACRL 4-phase quasi-adiabatic logic families have been done in this paper. In addition, a new resettable quasi-adiabatic flip-flop circuit is proposed for each of them. Using the non-resettable and the proposed resettable adiabatic flip-flops, a practical sequential circuit comprising of a 2-bit twisted ring counter is designed and the energy consumption, for four distinct states, at different ramping times is measured. The simulation results show that the energy consumption of the resettable counter is comparable with its non-resettable counterparts. Moreover, amongst the adiabatic logic used, the PFAL based implementation of both the non-resettable and the resettable counters exhibits the least energy consumption at all ramping times.
7 citations
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01 Oct 2016
TL;DR: The carry chain approach is presented, based on the use of the carry chain for determining the delay steps, which allows a very fine resolution and yields a fine-grain delay control with acceptable jitter.
Abstract: The experimental metastability characterizationof a flip flop requires a controllable delay with low jitter andhigh time resolution. In FPGAs such an experiment can bevery useful for in-situ or even online characterization of agiven flip flop, but existing solutions rely on the availability ofa digital clock manager (DCM) or a phase locked loop (PLL) for implementing this controllable delay. Given that such acomponent may not always be available, and that its linearityis sometimes sub-optimal and hard to calibrate, we present analternative approach in this paper. It is based on the use ofthe carry chain for determining the delay steps, which allows avery fine resolution. For calibration of the step sizes we proposeto operate the delay line in a ring oscillator whose frequencyis then measured for all delay settings. Our results show thatthis solution yields a fine-grain delay control with acceptablejitter. We demonstrate the usefulness of our approach in thecontext of a complete metastability characterization that nowcan be performed without requiring a DCM or PLL.
7 citations
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01 Apr 2016TL;DR: All Optical JK Flip Flop is proposed and demonstrated in this paper and a strategy of Optical pulse propagation in SOA based on XGM and FWM effects is shown.
Abstract: For photonic Digital processing All Optical Flip Flops are the major elements. External clock is the most important feature in Digital Signal Processing. All Optical JK Flip Flop is proposed and demonstrated in this paper. Based on the non linearity of Semiconductor Optical Amplifier (SOA) the principle of All Optical JK Flip Flop is designed. In this model we show a strategy of Optical pulse propagation in SOA based on XGM and FWM effects. The Logic is used to implement all Optical Flip-Flop, and its function is verified with the help of truth table. The whole setup is implemented with the help of Optisystem software which is one of the powerful software for analyzing the components. The full design is simple, compact, economical, thermally stable and integration capable.
7 citations
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01 Nov 2016TL;DR: The paper demonstrates the circuit of a low power D flip-flop serial in/parallel out (DFF SIPO) based shift register design and shows how the higher rate of circuit activity can help reduce transition times that are from the input to the output phases.
Abstract: The paper demonstrates the circuit of a low power D flip-flop serial in/parallel out (DFF SIPO) based shift register design. The flip-flops (FF's) consumption of casual logic power in a SoC chip (system on chip) commonly overpasses 50% as long the input and the output are in the same state thanks to the redundancy transition of interior loops. Conventional implementation of shift register systems such as linear feedback shift registers (LFSR) have two main drawbacks namely that elements into structure have been clocked during every clock cycle, and throughput is confined to just one (1) bit per clock cycle. Large scale integrated systems have much higher power consumption when tested due to the increased level of circuit activity. The higher rate of circuit activity can help reduce transition times that are from the input to the output phases. Flip-flops have been performed in 0.18μm CMOS technology. Circuit simulations with displays showing appropriate power dissipations have been reduced are possible where input signals decrease switching activities. A 16-Bit shift register is shown as an easy low power usage.
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TL;DR: Novel applications of RFF in randomness preserving frequency division, random frequency synthesis, and random number generation are demonstrated.
Abstract: In this work, a new type of elementary logic circuit, named random flip-flop (RFF), is proposed, experimentally realized, and studied. Unlike conventional Boolean logic circuits whose action is deterministic and highly reproducible, the action of a RFF is intentionally made maximally unpredictable and, in the proposed realization, derived from a fundamentally random process of emission and detection of light quanta. We demonstrate novel applications of RFF in randomness preserving frequency division, random frequency synthesis, and random number generation. Possible usages of these applications in the information and communication technology, cryptographic hardware, and testing equipment are discussed.
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04 Jul 2016
TL;DR: A low power, high speed and cost efficient 4 bit Johnson counter is proposed and performance and cost of the proposed counter is compared against the conventional counter.
Abstract: Sequential circuits largely contribute to the power dissipation and propagation delay in a digital system. Low power, less delay and area efficient sequential circuit design has been the major concern for VLSI designers. The selection of optimized design technology plays a key role in achieving the above parameters. A counter is a sequential circuit having wide application area in microcontroller circuits including PLL, Digital to Analog converters, signal generators, signal synthesizers etc. In this paper a low power, high speed and cost efficient 4 bit Johnson counter is proposed. Deployed flip flop circuit uses 14 transistors to realize the negative edge triggered master slave D flip flop operation. Performance and cost of the proposed counter is compared against the conventional counter. The proposed design is found 48.86 % faster with having 43.22 % lesser power dissipation than conventional design. The transistor requirements in the proposed counter is also 69.5 % lesser making it an optimized design in terms of area.
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01 May 2016TL;DR: Through bypassing the slave latch during loading/unloading operation the proposed design eliminates redundant switching activity in combinational logic and hence minimizes test power and the functional performance overhead is comparatively very less than the previously proposed output gating techniques.
Abstract: Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified scan flip-flop design which uses a low cost dynamic slave latch to shift the test vectors and allows the static slave latch to retain the responses from the previous test vector. Through bypassing the slave latch during loading/unloading operation the proposed design eliminates redundant switching activity in combinational logic and hence minimizes test power. Furthermore the proposed scan flip flop design does not use any gating element in functional path, and hence the functional performance overhead is comparatively very less than the previously proposed output gating techniques so far.
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06 Apr 2016TL;DR: In this article, the design and performance analysis of 5 transistor (5T) TSPC D Flip-flop with respect to transistor density, power, and delay are presented and simulated using Cadence Virtuoso Platform, with gpdk 180nm process using 1.8V supply voltage.
Abstract: True Single Phase Clock (TSPC) is a general dynamic flip-flop that operates at high speed and consumes low power. This paper describes the design and performance analysis of 5 transistor (5T) TSPC D Flip-flop in comparision with different TSPC D Flip-flops such as; (i) MS-Negative-edge triggered TSPC D Flip-flop, (ii) Positive-edge triggered TSPC D Flip-flop with (a) 13 transistors, (b) 11 transistors, (c) 9 transistors, (d) 8 transistors, (e) 6 transistor TSPC D Flip-flops with respect to transistor density, power and delay. Finally Charge Pump with PFD is designed using 5T TSPC D Flip-flop method and functionality of the circuit is verified through simulation. A Layout of 5T TSPC D Flip-flop and Charge Pump with PFD are designed. DRC, ERC, LVS are verified with gpdk 180nm technology. All the circuits used in this paper are designed and simulated using Cadence Virtuoso Platform, with gpdk 180nm CMOS process using 1.8V supply voltage.
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TL;DR: In this paper, the authors numerically demonstrate a new extraction scheme for generating ultra-fast physically random sequence of bits using a dual-channel optical chaos source with suppressed time delayed (TD) signature in both the intensity and the phase of its two channels.
Abstract: In this paper, we numerically demonstrate a new extraction scheme for generating ultra-fast physically random sequence of bits. For this purpose, we utilize a dual-channel optical chaos source with suppressed time delayed (TD) signature in both the intensity and the phase of its two channels. The proposed technique uses M 1-bit analog-to-digital converters (ADCs) to compare the level of the chaotic intensity signal at time t with its levels after incommensurable delay-interval Tm, where m = {1,2, … , M}. The binary output of each 1-bit ADC is then sampled by a positive-edge-triggered D flip flop. The clock sequence applied to the flip-flops is relatively delayed such that the rising edge of the clock triggering the m flip-flop precedes the rising edge of the clock of a subsequent m+1 flip-flop by a fixed period. The outputs of all flip flops are then combined by means of a parity-check logic. Numerical simulations are carried out using values of parameters at which TD signature is suppressed for chosen values of setup parameters. The 15 statistical tests in Special Publication 800-22 from NIST are applied to the generated random bits in order to examine the randomness quality of these bits for different values of M. The results show that all tests are passed from M = 1 to M = 39 at sampling rate up to 34.5 GHz which indicates that the maximum generation rate of random bits is 2.691 Tb/sec using a chaotic source of single VCSEL and without employing any pre-processing techniques.
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TL;DR: A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme that is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities is proposed.
Abstract: A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme condi- tionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.
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01 Oct 2016TL;DR: The results show that the designed ternary explicit pulsed JKL flip-flop has correct logic function and low power consumption.
Abstract: A novel single-edge explicit pulsed JKL flip-flop (S-JKL) and dual-edge explicit pulsed JKL flip-flop (D-JKL) are designed with Carbon Nanotube Field Effect Transistor (CNFET). Firstly, a single-edge pulsed generator (S-PG) is designed. Then combined with a ternary JKL latch, a S-JKL is obtained; D-JKL is designed by replacing S-PG with double-edge pulsed generator (D-PG). The circuits possess the character of high speed and low power by employing CNFET. The scheme is simulated by HSPICE, and the results show that the designed ternary explicit pulsed JKL flip-flop has correct logic function and low power consumption.
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01 Sep 2016TL;DR: The performance of ring counter is improved using pulsed latch technique and overall there is an improvement in power delay product.
Abstract: In this work, the performance of ring counter is improved using pulsed latch technique. In high speed and low power VLSI applications where heavy pipelining is used, there is requirement of low power edge triggered flip flops. The migration from flip flop to pulsed latch has become great success in low power VLSI application. The proposed circuit has been designed using Cadence Virtuoso in 90 nm CMOS technology. The pulse latch technique reduces the power consumption significantly in the designed circuit and overall there is an improvement in power delay product. The proposed circuit also require less number of transistors for its implementation as compared to conventional version.
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08 Apr 2016
TL;DR: A new D flip flop design is proposed which employs improved SVL technique in order to reduce power consumption due to leakage currents in standby mode and uses less number of clocked transistors, thus reduces the dynamic power consumption as well as delay compared to existing design.
Abstract: D flip flops are extensively used in analog, digital and mixed signal systems. D flip flops are first choice to realize different counters, shift registers and other circuits. One major consequence of scaling of CMOS technology is leakage power. To decrease power consumption and to improve life time of battery, the voltage supplied to the given circuit during standby mode should be reduced. This paper proposes a new D flip flop design which employs improved SVL technique in order to reduce power consumption due to leakage currents in standby mode. Also the proposed design uses less number of clocked transistors, thus reduces the dynamic power consumption as well as delay compared to existing design. Proposed design achieves 60.54% reduction in power delay product in comparison with existing D flip flop design. Both existing design and proposed design are simulated using Tanner T spice tool at 45nm technology.
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09 Nov 2016
TL;DR: In this paper, an automatic reset structure for a clock switching process, comprising a time delay unit D, an exclusive-Or gate XOR, a first inverter INV1 and a second inverter INV2, an AND gate AND, a counter CT and a RS flip flop FF, was presented.
Abstract: The invention discloses an automatic reset structure for a clock switching process, comprising a time delay unit D, an exclusive-Or gate XOR, a first inverter INV1 and a second inverter INV2, an AND gate AND, a counter CT and a RS flip flop FF. The time delay unit D and the exclusive-Or gate XOR form a high level pulse generation circuit, and the high level pulse generation circuit is used for providing a clear signal of an asynchronous clear end Clr of the counter CT and a setting signal of a setting end S of the RS flip flop FF so as to generate a high level Rst reset signal; the first inverter INV1, the second inverter INV2 and the AND gate AND form a gated clock structure, and the gated clock structure is used for controlling a clock signal input by a clock input end CP of the counter CT; and when an output top digit QD of the counter CT outputs high level, the RS flip flop FF resets, and the Rst reset signal is removed. The automatic reset structure for the clock switching process can automatically output the reset signal when a clock selection signal changes; and when clock switching is completed, the automatic reset structure for the clock switching process automatically removes the reset signal, and thus, a controlled circuit is enabled to work normally.
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TL;DR: An approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D-type flip flop, which results in a very small static phase error between the reference clock and feedback clock.
Abstract: Summary
In conventional delay-locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D-type flip flop. The setup time of D-type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 µm CMOS process design, with a reference frequency of 700 ~ 900 MHz. The active area is 0.031 mm2, and the phase error after correction is less than 5 ps. Copyright © 2015 John Wiley & Sons, Ltd.
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02 Jun 2016TL;DR: In this article, a low clock power data-gated flip-flop with an exclusive OR component including a first exclusive OR, a second exclusive OR and a first OR output is presented.
Abstract: A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.
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18 Feb 2016TL;DR: In this paper, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches, which operate as storage elements and are coupled to the pulse generator.
Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.
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01 Oct 2016
TL;DR: The authors here render a heuristic approach in developing ternary gates and flip-flops and ratify that such models are completely trustworthy and it accord perfectly with next generation computing having the merits of higher information storing capacity and thereby minimizing interconnections.
Abstract: Succeeding the Moore's law CMOS technology accumulated extreme device complexity with larger interconnects. But owing to physical scaling limitations CMOS technology itself is degrading the overall performance of binary logic ICs. This has augmented the urgency of Multi Valued Logic (MVL). A ternary logic or a three-valued logic is contemplated as the noblest radix of all assorted MVL formulates. The synthesis of ternary future ready logic circuits is itself a benchmark in device research arena. Yet there sustain ample research dearth to realize ternary hardware to meet the common needs of basic living. To cope up with such pivotal necessitates the authors here render a heuristic approach in developing ternary gates and flip-flops. Besides, Single Electronic technology is incorporated to further enhance the novel nature of the models in this paper. Initially the Single Electron ternary gates andflip-flops are simulated using Monte Carlo based SIMON 2.0 simulator and the simulation results exhibit a simple structure with less propagation delay and lower power consumption compared to conventional CMOS topology. Further it also ratify that such models are completely trustworthy and it accord perfectly with next generation computing having the merits of higher information storing capacity and thereby minimizing interconnections. Eventually more transistors can be cramped into the reduced chip dia in order to enhance the performance of SET MVL circuits.
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01 Apr 2016TL;DR: Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed design features the best power-delay product performance in all FF designs under comparison.
Abstract: In this work, a low power dual edge triggered flip flop design using multi threshold CMOS is proposed. Proposed Flip-Flop (FF) has three new feature points. First point, the pulse generation control logic is designed with EXOR gate and inverter chain which reduces the complexity and extra switching in pulse generator circuit. Second point, signal feed through technique with some modification is devised to speed up the charging and discharging along the critical path only when needed. Third point, multi-threshold CMOS technique is also applied to get low power dissipation. As a result, no. of transistors in pulse-generation circuit has been reduced for power and area saving. Various post layout simulation results based on CMOS 90-nm technology reveal that the proposed design features the best power-delay product performance in all FF designs under comparison.
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13 May 2016TL;DR: The proposed circuit designs are superior to the existing designs in terms of number of gates, garbage outputs and quantum costs and the proposed designs are fault tolerant.
Abstract: Irreversible computing requires consumption of energy to obtain missing bits due to overlapped mapping between input and output vectors. For this reason, reversible computing has become one of the most significant computing processes for the forthcoming computing technology as they dissipate very low power. Therefore, a major research objective in this field is the synthesis of different types of reversible latches and flip flops. A parity preserving reversible new gate is proposed in this paper. A modification of existing Peres gate is also proposed. Using the proposed gates, the conventional flip flops — RS flip flop, JK flip flop, D flip flop and T flip flop are designed. Therefore, the proposed designs are fault tolerant. The master-slave JK flip flop and master-slave D flip flop are also designed using the proposed gates. The proposed circuit designs are superior to the existing designs in terms of number of gates, garbage outputs and quantum costs.
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12 Apr 2016
TL;DR: In this paper, a scan flip flop with a cross couple structure has been proposed, which includes a first and a second tri-state inverters sharing a first output node and facing each other, and latches the internal signal according to a clock signal.
Abstract: To improve space efficiency, a scan flip flop according to the present disclosure includes: an input part which selects any one of a data input signal and a scan input signal according to an operation mode and provides it as an internal signal; and a flip flop which has a cross couple structure which includes a first and a second tri-state inverters sharing a first output node and facing each other, and latches the internal signal according to a clock signal.
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29 Sep 2016TL;DR: In this paper, a multi-level conversion flip-flop circuit for multi-power domain integrated circuits (ICs) and related methods are disclosed, where the data control transistor is configured to activate the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to a clock signal.
Abstract: Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs) and related methods are disclosed. A flip-flop circuit latches a representation of a received input data signal in a lower voltage domain, in a latch circuit in a higher voltage domain without need for separate voltage level shifters. As a result, insertion loss/delay is minimized, thereby increasing performance. In certain aspects, the flip-flop circuits employ a gate-controlled, data control transistor to control activation of the latch circuit. By coupling the input data signal to a gate of the data control transistor, the input data signal in the lower voltage domain is not directly latched into the latch circuit. Instead, the data control transistor is configured to activate the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to a clock signal.
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28 Dec 2016TL;DR: In this article, a flip-flop circuit with low-leakage transistors is proposed to pass a data signal for the logic circuit along a signal path, and a capacitor is coupled between the signal path and ground to store a value of the data signal.
Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.