Showing papers on "Flip-flop published in 2017"

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

Abstract: In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master–slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and complementary pass-transistor logic. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high power and delay performance. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. In this design, a virtual $V_{{\mathrm{DD}}}$ design technique, which facilitates a faster state transition in the slave latch, is devised to enhance time performance. In circuit implementation, transistor sizes are optimized with respect to the power-delay product (PDP). A TSMC 90-nm CMOS process was selected as the implementation technology. In this paper, the performance levels of seven FF designs were compared. The timing parameters of each FF were first characterized. Post-layout simulation results indicated that the proposed design excelled in various performance indices such as PDP, clock-to-Q delay, average power consumption, and leakage power consumption. Moreover, the design was determined to have the smallest layout area. Compared with the conventional transmission-gate-based FF design, the PDP improvement in the proposed design was up to 63.5% (at 12.5% switching activity) and the area saving was approximately 10%. Further simulations on process corners, supply voltage settings, and working frequencies were conducted to study the design reliability.

Reversible Flip-Flops in Quantum-Dot Cellular Automata

Abstract: Quantum-dot cellular automata is a new technology to design the efficient combinational and sequential circuits at the nano-scale. This technology has many desirable advantages compared to the CMOS technology such as low power consumption, less occupation area and low latency. These features make it suitable for use in flip-flop design. In this paper, with knowing the characteristics of reversible logic, we design new structures for flip-flops. The operations of these structures are evaluated with QCADesigner Version 2.0.3 simulator. In addition, we calculate the power dissipation of these structures by QCAPro tool. The results illustrated that proposed structures are efficient compared to the previous ones.

Design and implementation of dynamic logic gates and R-S flip-flop using quasiperiodically driven Murali-Lakshmanan-Chua circuit.

Abstract: We report the propagation of a square wave signal in a quasi-periodically driven Murali-Lakshmanan-Chua (QPDMLC) circuit system. It is observed that signal propagation is possible only above a certain threshold strength of the square wave or digital signal and all the values above the threshold amplitude are termed as "region of signal propagation." Then, we extend this region of signal propagation to perform various logical operations like AND/NAND/OR/NOR and hence it is also designated as the "region of logical operation." Based on this region, we propose implementing the dynamic logic gates, namely, AND/NAND/OR/NOR, which can be decided by the asymmetrical input square waves without altering the system parameters. Further, we show that a single QPDMLC system will produce simultaneously two outputs which are complementary to each other. As a result, a single QPDMLC system yields either AND as well as NAND or OR as well as NOR gates simultaneously. Then, we combine the corresponding two QPDMLC systems in a cross-coupled way and report that its dynamics mimics that of fundamental R-S flip-flop circuit. All these phenomena have been explained with analytical solutions of the circuit equations characterizing the system and finally, the results are compared with the corresponding numerical and experimental analysis.

Compact Organic Complementary D-Type Flip-Flop Circuits Fabricated with Inkjet Printing

Abstract: Organic thin-film transistors (OTFTs) have received significant consideration in recent years for potential deployment in low-cost and large-area printed electronics. D-type flip-flop (D-FF) circuits are one of the most important logic gates for data processing and storage in such applications. Previous work has reported on NAND-based organic D-FF circuits. Although the demonstrated printed circuits exhibit low voltage operation at 10 V, each D-FF circuit requires 34 TFT devices and occupies an area of 192 mm2 per D-FF circuit. This paper demonstrates inkjet-printed organic D-FF circuits with a compact circuit design using clocked inverters and transmission gates and compares the occupied area and the circuit performance with those of NAND-based organic D-FF circuits. The compact organic D-FF circuits require only 18 OTFT devices, and can use 60% less area than NAND-based organic D-FF circuits fabricated by the same process. In addition, the compact organic D-FF circuits exhibit a shorter propagation delay time than the NAND-based D-FF circuits. The mechanism for the shortened delay time will be discussed in detail, based on SPICE simulations. These results demonstrate the high potential of these compact organic D-FF circuits in printable electronics.

Memristor-based nonvolatile synchronous flip-flop circuits

Abstract: Flip-flops are basic units for all kinds of sequential logic circuits and complex digital electronics systems, which can be used to store binary data owing to their two stable logic states 0 and 1. SR flip-flop and D flip-flop are widely employed in digital circuits as representative types of basic flip-flops. In this paper, logic circuits of nonvolatile synchronous SR flip-flop and D flip-flop are proposed, which utilize nanoscale memristors as the nonvolatile memory elements to store the information with different conductance states. The resistive switching property of memristors is well-suited for implementing trigger function in flip-flop circuits. Compared with traditional flip-flop ones, the proposed memristor-based SR flip-flop and D flip-flop have nonvolatile characteristic, which is suitable for occasions with unstable power supply. Meanwhile, the designed circuits provide experimental references for the development of digital circuit structures based on the feasibility of tight integration of memristors with CMOS circuitry.

Design and implementation of dynamic logic gates and R-S flip-flop using quasiperiodically driven Murali-Lakshmanan-Chua circuit

Abstract: We report the propagation of a square wave signal in a quasi-periodically driven Murali-Lakshmanan-Chua (QPDMLC) circuit system. It is observed that signal propagation is possible only above a certain threshold strength of the square wave or digital signal and all the values above the threshold amplitude are termed as 'region of signal propagation'. Then, we extend this region of signal propagation to perform various logical operations like AND/NAND/OR/NOR and hence it is also designated as the 'region of logical operation'. Based on this region, we propose implementing the dynamic logic gates, namely AND/NAND/OR/NOR, which can be decided by the asymmetrical input square waves without altering the system parameters. Further, we show that a single QPDMLC system will produce simultaneously two outputs which are complementary to each other. As a result, a single QPDMLC system yields either AND as well as NAND or OR as well as NOR gates simultaneously. Then we combine the corresponding two QPDMLC systems in a cross-coupled way and report that its dynamics mimics that of fundamental R-S flip-flop circuit. All these phenomena have been explained with analytical solutions of the circuit equations characterizing the system and finally the results are compared with the corresponding numerical and experimental analysis.

Design of frequency-encoded data-based optical master-slave-JK flip-flop using polarization switch

Abstract: An optical data processing and communication system provides enormous potential bandwidth and a very high processing speed, and it can fulfill the demands of the present generation. For an optical computing system, several data processing units that work in the optical domain are essential. Memory elements are undoubtedly essential to storing any information. Optical flip-flops can store one bit of optical information. From these flip-flop registers, counters can be developed. Here, the authors proposed an optical master-slave (MS)-JK flip-flop with the help of two-input and three-input optical NAND gates. Optical NAND gates have been developed using semiconductor optical amplifiers (SOAs). The nonlinear polarization switching property of an SOA has been exploited here, and it acts as a polarization switch in the proposed scheme. A frequency encoding technique is adopted for representing data. A specific frequency of an optical signal represents a binary data bit. This technique of data representation is helpful because frequency is the fundamental property of a signal, and it remains unaltered during reflection, refraction, absorption, etc. throughout the data propagation. The simulated results enhance the admissibility of the scheme.

Investigation on photonic crystal based all-optical clocked D-flip flop

Abstract: In this study, the authors propose a photonic crystal-based clocked D-flip flop using multi-mode interference (MMI). A central MMI waveguide is created for the interference of the input light and ports are placed at both input and output ends of it. The proposed structure is resulted with a contrast ratio (CR) of 9.63 and 5.84 dB at the outputs Q and QQ with a response time or delay of less than 0.29 ps. Furthermore, the input and output waveguides are extended with sharp and smooth bend waveguides, respectively, in order to increase the delay of the structure as the delayed output is one of the main objectives of D-flip flop. The modified D-flip flop structure is operated with a delay of more than twofold of the basic structure by maintaining nearly the same CR at the output. The compactness and the fair simulation results of the proposed structure show that it is quite suitable to be a part of photonic integrated circuit.

Dynamic current mode logic based flip-flop design for robust and low-power security integrated circuits

Abstract: Side-channel analysis (SCA) is a powerful technique to reveal the secrets using detectable physical leakages from logic elements, which brings severe security threats to modern circuits. To alleviate this problem, applying cell-level countermeasure is usually a suitable solution, which is mainly implemented as dual-rail precharge logic. Mace et al. has the proposed dynamic current mode logic (DyCML) scheme as a novel technology to resist SCA, whose power consumption is constant regardless of the data processed. However, the DyCML-based sequential elements are still in blank field. So, we have implemented a novel flip-flop compatible with DyCML, whose enhanced security has been proved by corresponding simulations.

Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits

Abstract: Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking SEU-hardened FFs benefit less from temporal masking than conventional FFs Circuit hardening implications for SEU-hardened and unhardened FFs are discussed

Design of a low-power nonvolatile flip-flop using three-terminal magnetic-tunnel-junction-based self-terminated mechanism

Abstract: A nonvolatile flip-flop (NV-FF) using a three-terminal magnetic tunnel junction (3T-MTJ)-based self-terminated mechanism is proposed for a low-power logic LSI while maintaining almost the same performance as a conventional CMOS-based logic LSI. The use of a self-terminated mechanism, which continuously monitors the change in MTJ resistance, makes it possible not only to minimize the write energy consumption for the 3T-MTJ device but also to ensure a reliable write. Moreover, since the write current path is separated from the read current path in the 3T-MTJ device, the sensing circuit and the write driver are individually optimized, which makes it possible to minimize the performance overhead due to additional components. As a result, the write energy of the proposed NV-FF is reduced by 69% with a small performance overhead compared with that of a conventional NV-FF using a worst-case-oriented writing scheme.

Implementation of power efficient 8-bit reversible linear feedback shift register for BIST

Abstract: Built-in Self Test (BIST) is more appropriate for testing any VLSI circuits as it provides a larger range for low power applications. Test pattern generator is the vital module in BIST. Linear Feedback Shift Registers (LFSR) is broadly used in BIST for generating test vectors as it produces highly random test pattern. This paper mainly aims at design and implementation of power efficient LFSR using reversible logic for low power applications. Pareek Gate is used to implement reversible D Flip Flop (DFF). 8 bit reversible LFSR is implemented using 8 DFFs, 8 Feynman Gates (FG) and 3 Double Feynman Gates (DFG). It is found from the analysis that, the proposed approach of designing reversible LFSR reduces the power by 10% when compared to conventional design. Thus the proposed design can be used for designing BIST in low power applications.

A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits

Abstract: Side channel attacks have become a major threat to hardware systems. Most modern digital IC designs utilize sequential elements which dominate the information leakage. This paper reports the first unified analysis and comprehensive comparison of known secure flip-flop circuits. We present a device level analysis of the information leakage from these FFs and propose several evaluation metrics to quantify their security. We show that simulated PA attacks that utilize the information evaluated by these metrics at the gate-level extract more information at the module-level.

RS flip-flop implementation based on all spin logic devices

Abstract: All spin logic (ASL) device is one of the promising post-CMOS candidates. Owing to unique features such as non-volatility, simple configuration, ultra-low-switching energy, and good scalability, ASL devices can be exploited in logic applications. Based on the characteristics of non-volatility and bistable states of ASL device, an RS flip-flop is proposed which is composed of seven ASL devices and employs a complementary clock signal scheme. Using the coupled spin-transport/magneto-dynamics model, validity of its logic operation is demonstrated. As a fundamental building block of sequential logic circuits, the proposed RS flip-flop will be an useful component for designing large-scale ASL sequential logic circuits.

Design of high frequency D flip flop circuit for phase detector application

Abstract: A low power, high frequency positive edge D flip flop circuit is implemented. Its operating frequency is 5GHz with a supply voltage of 1.8 V produces a output at a positive edge triggered signal. It consists of 16 transistor which compel low power of 10.42 μW with a phase noise of −147dBc/Hz and output noise −154.77dB at offset frequency 1 MHz, Circuits is also tested at different corner frequency and has minimal area of 88.571μmm2 simulation of results is done by cadence tools in 90nm CMOS process The proposed D flip flop has outplayed the prior research in terms of performance metrics.

Frequency acquisition technique for injection-locked clock generator using asynchronous-sampling frequency detection

Abstract: An injection-locked clock generator with a frequency acquisition scheme, which eliminates a conflict between the injection and the frequency acquisition loop is described. In the proposed frequency detector (FD), the oscillator clock is sampled by the reference clock, which, respectively, becomes asynchronous sampling and synchronous sampling before and after injection locking. By taking advantage of this aspect, the proposed FD does not generate any active output once the oscillator is injection-locked, and therefore the conflict is completely resolved. Moreover, it is not turned off but just produces no output, hence it can immediately react to a sudden loss of injection-locking. The FD is implemented with a low hardware overhead of only six flip-flops and a few logic gates. The validity of the feasibility of the proposed scheme is verified by a circuit simulation.

A low cost robust radiation hardened flip-flop circuit

Abstract: A new radiation hardened flip-flop, named low power single-phase clocked rad-hard flip flop, is proposed. The structure is based on robust differential-input latches working on a single-phase clock, which allows a reduction in the number of nodes sensitive to radiation. The proposed structure optimizes area and power and offers better performance, as compared to state-of-the-art techniques. Experimental results from test chip manufactured in a 180-nm BCD technology exposed to heavy ions, neutrons and alpha particles show that the proposed structure significantly reduces single event upsets (SEU).

Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital vlsi designs

Abstract: This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool

Abstract: This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.

Design of a D flip flop for optimization of power dissipation using GDI technique

Abstract: It is aimed to present the methodology used for of optimization of power consumed by a D flip flop using gate diffusion input technique using the gate clocking methodology. A further 1.38% optimization is obtained by using this method, of the already optimized GDI D flip flop circuit using D flip flop triggered on single edge of clock. The Gate diffusion technique is used after analyzing a number of D flip flop circuits since it is found to give the lowest power delay product as compared to other CMOS configurations.

Single Flip-Flop Driving Circuit for Glitch-Free NAND-Based Digitally Controlled Delay-Lines

Abstract: NAND-based digitally controlled delay-lines (DCDLs) are employed in several applications owing to their excellent linearity, good resolution and easy standard cell design. A glitch-free DCDL behavior is often a strict requirement [e.g. spread-spectrum clock generators (SSCG) and digitally controlled oscillators]. Existing glitch-free NAND-based DCDL topologies either require two flip-flops for each DCDL delay-element (DE) or present a very long settling time which limits the maximum working frequency. This paper proposes a novel glitch-free NAND-based DCDL that joins the advantages of previously proposed topologies: uses only a single flip-flop for each DE (reducing area and power) and has relaxed timing requirements (allowing easy integration in applications like SSCG). In the paper, the glitch-free operation of the proposed circuit is firstly demonstrated theoretically and then verified experimentally, with the help of an SSCG built using proposed DCDL and implemented in 28 nm CMOS. Simulation results show that proposed DCDL results in a more that 30 % reduction of the power dissipation and a >20 % reduction in area occupation with respect to double flip-flop DCDL, without any timing constraints penalty.

Design of Radiated Comb Generator Using Single-Ended Positive Emitter Coupled Logic (PECL) D Flip-Flop

Abstract: Comb generator has been an indispensable tool in the electromagnetic compatibility (EMC) testing field. It is used for calibration and self checking of the test systems. This paper presents a rarely explored yet promising radiated comb generator that makes use of a single-ended PECL D Flip-Flop as the pulse forming component. Measurements show that the generated pulses typically possess fall time and rise time of 330 ps and 410 ps, respectively. Its frequency accuracy is offset by +24 ppm, which is common for crystal oscillators. When being connected to a monopole rod antenna, the comb generator is able to generate radiated emissions that have smooth envelope profile up to 1000 MHz frequency range.

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core

Abstract: In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account sensing delay, dynamic power, leakage power and process variations. Results show that the transmission gate pulsed latch (TGPL) based NVFF exhibits enhanced performance compared to conventional master-slave structure, with improved variability, 15.7% fast timing metric, 76% dynamic, 79% leakage power reduction and 30% layout area reduction in multi-bit NV-FF hybrid circuit integration. The pulsed latch FF core can enhance NVFF scalability with increased energy-delay and layout efficiency, as well as reduced active and leakage energy.

Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process

Abstract: The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints.

Implementation of shift register using pulsed latches

Abstract: Low power and less area in an electronics devices having very high demand in the world because of user want to fast mobility with less power consumption and also not compromising with the area By using multiple stages of flip flop and latches to compare area and power The main objective to designing a flip-flop with respective pulse latches is consume less power For solving timing problem a new technique is use, in which of pulsed latches and multiple non-overlapping delayed version of pulsed clock signal are uses In this system, single clock pulse signal uses and combine this latches to multiple sub-shifter register and further for only a limited period of time storage latches In this minimum number of clock pulse signal use by groping latches to multiple sub shift register and using short-term storage latches 8, 16, 32, upto 256-bit shift register using pulsed latches was fabricated using 180nm cmos process with vdd is 18V This proposed system implementation by using cadence tool

Implementation and Designing of Low Power SR Flip-Flop Using 45NM CMOS Technology

Abstract: The design of low-power devices is currently an important area of research due to an increase in demand for portable devices.Since the MOS device is widespread, there is a great need for circuits to consume less power, especially for portable and handheld devices. A memory element consumes 70 percent of the total power in an integrated circuit. As flip-flop is the primary place of memory elements to use on any portable device, a wide attention to reduce energy consumption flip-flop will help reducing energy consumption in a large IC. In this paper, we designed a flip-flop with CMOS logic; It consumes less energy than conventional gates designed. Switching transistors occurs when applied input clock is applied. Proposed SR flip-flop synchronization, 0.7V power dissipation transient analysis, and SR flip-flop different applications. This flip-flop is implemented using 45 nm in virtuoso cadence.

Analytical study of high performance flip-flop circuits based on performance measurements

Abstract: In designing synchronous circuits and memory elements, Flip-flops (FF) play an integral role. In the present era, the demand of area efficient, lesser delay, and faster devices are the major concern. This paper present the comparative study of Flip Flops in terms of area and delay. The problem of device size is very dominant today because the demand for small device size along with lesser number of transistors is increasing. And also for implementing a circuit, comparatively less number of transistors are preferred in comparison to conventionally used number of transistors, as it results in lesser number of switching activities. And smaller delay is preferred as it results in faster device along with faster response time of device. Hence, in this paper, the comparative study of various flip flops using The Clocked CMOS (C2MOS) register, True Single-Phase Clocked Register (TSPCR), Self-Gating Flip Flop, Static Flip Flop is done. The reduction in the delay is done by properly changing the size of transistor and alteration in the value of voltage. The circuits are simulated and correlated using 45nm technology.