Showing papers on "Flip-flop published in 2019"

Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Abstract: Flip-flops (FFs) are essential building blocks of sequential digital circuits but typically occupy a substantial proportion of chip area and consume significant amounts of power. This paper proposes 18-transistor single-phase clocked (18TSPC), a new topology of fully static contention-free single-phase clocked (SPC) FF with only 18 transistors, the lowest number reported for this type. Implemented in 65-nm CMOS, it achieves 20% cell area reduction compared to the conventional transmission gate FF (TGFF). Simulation results show the proposed 18TSPC is two times more efficient than TGFF in the energy-delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6 V, 25 °C show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.

Nonvolatile Spin-Based Radiation Hardened Retention Latch and Flip-Flop

Abstract: Reduction of leakage power and vulnerability to radiation are of critical challenges in modern nanometer CMOS technologies because of scaling down requirement. Spintronic logic has been progressed to realize these demands based on magnetic-based elements properties especially magnetic tunnel junction (MTJ) such as radiation-hardened, non-volatility, and CMOS process compatibility. A novel soft-error tolerant and highly reliable latch circuit is proposed in this paper which is a promising choice for reliable and low-power architectures. Furthermore, employing the proposed shadow latch based on MTJ cells as a backup structure along with the rad-hard main latch is aimed to the realization of a nonvolatile and SEU-immune flip-flop which is applicable in next-generation CMOS circuits. Simulations of proposed circuits have been performed by SPICE tool and a 45 nm CMOS technology model to evaluate the effectiveness of topologies.

Design of Multiplexer-Based D Flip-Flop with Set and Reset Ability in Quantum Dot Cellular Automata Nanotechnology

Abstract: Despite many advances in the electronics industry, much effort is being made to improve existing technologies. One of the proposed technologies in this field is the Quantum Cellular Automata (QCA), which provides low power, low area, high density, and high-speed structures. Latches and flip-flops are always the most commonly used circuits in digital design, and designing these structures with greater stability and capability is very important. In this paper, with the use of the appropriate D latch in terms of volume and delay, the edge sensitive D flip-flops in the QCA technology are introduced with the ability of set and reset based on optimized multiplexer design. The simulation results show that the proposed designs are stable and useful structures in terms of area, delay and complexity and are suitable for use in the larger circuits. For example proposed synchronous rising edge D flip-flop with set and reset pins has 74 quantum cells, 2.5 clock cycles delay and 0.09μm2 occupied area.

Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

Abstract: Reducing the power consumption and scaling the devices are the important concerns of today's electronics. Flip-Flop (FF) is one of the basic elements in electronic devices. Thus, the performance of the electronic devices is improved by improving these qualities in the FFs. In this paper, a novel pulse-triggered CNTFET-based D-Flip-Flop structure is proposed. This structure utilizes signal feed through technique to reduce the “0” to “1” transition, which requires only one CNTFET. Moreover, the discharging path is optimized to reduce the delay time for “1” to “0” transition by using only two CNTFETs. The novel structure is simulated in Hspice using Stanford model. The output results prove that the performance of the proposed structure is improved greatly in terms of power consumption, D-to-Q delay, the power-delay product, and the number of required transistors in comparison with other pulse-triggered Flip-Flop structures.

Non-Volatile Spintronic Flip-Flop Design for Energy-Efficient SEU and DNU Resilience

Abstract: In this paper, low-energy radiation-hardening approaches are proposed to develop non-volatile (NV) flip-flop (FF) circuits using spintronic devices. In particular, spin Hall effect magnetic tunnel junctions are used to design a radiation-hardened NV-latch that is proposed to be utilized as a shadow latch to maintain the data during the standby mode when the circuit is power-gated. Moreover, soft-error resilient complementary metal–oxide–semiconductor-based latching circuits are designed to be leveraged as master and slave latches in the NVFF structure. The proposed hardening techniques are based on using feedback loops and clock-gating Muller C-elements, as well as increasing the charge capacity of the vulnerable nodes. The circuit simulations indicate that the proposed single-event upset and double node upset resilient latching circuits can achieve at least 81% and 24% power-delay product improvement, respectively, while incurring comparable area overhead compared to the previous energy-efficient radiation-hardened latch designs. Finally, the proposed latching circuits are combined to develop four radiation-hardened NVFF designs. The results obtained show that, using the proposed NV latching circuit as a shadow latch can result in two orders of magnitude reduction in energy consumption compared to the FF circuits with an NV master latch. In addition, the proposed latches achieve favorable tradeoffs in terms of minimized performance overheads and maximized robustness (100%) of soft fault coverage to single and double upsets. Thus, the proposed NVFFs can be employed within logic datapaths to ensure data integrity as a potential mainstream solution for aerospace and avionic nanoelectronics.

All-optical majority gate based on an injection-locked laser.

Abstract: An all-optical computer has remained an elusive concept. To construct a practical computing primitive equivalent to an electronic Boolean logic, one should utilize nonlinearity that overcomes weaknesses that plague many optical processing schemes. An advantageous nonlinearity provides a complete set of logic operations and allows cascaded operations without changes in wavelength or in signal encoding format. Here we demonstrate an all-optical majority gate based on a vertical-cavity surface-emitting laser (VCSEL). Using emulated signal coupling, the arrangement provides Bit Error Ratio (BER) of 10-6 at the rate of 1 GHz without changes in the wavelength or in the signal encoding format. Cascaded operation of the injection-locked laser majority gate is simulated on a full adder and a 3-bit ripple-carry adder circuits. Finally, utilizing the spin-flip model semiconductor laser rate equations, we prove that injection-locked lasers may perform normalization operations in the steady-state with an arbitrary linear state of polarization.

Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region

Abstract: For ultra-low-power Internet of Things (IoT) devices powered by batteries or energy harvesting, a nonvolatile flip-flop (NV-FF) operating in the near-threshold voltage (NTV) region has been widely studied to save both standby and active power. However, in the NTV region, the NV-FF suffers from restore yield and performance degradation due to the increase in process variation combined with the decrease in supply voltage. This paper presents a comparative analysis of the previous NV-FFs according to supply voltage scaling and suggests the design directions for implementing the NV-FF that can operate with compact area and high performance even in the NTV region. Through the comparative analysis, a novel offset-cancellation sensing-circuit (OCSC)-based NV-FF, which adopts a separate latch and sensing circuit structure and an offset-cancellation technique, is proposed. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm model parameters show that the proposed NV-FF satisfies a target restore yield with 32% area, 88% speed, and 82% energy savings in comparison with a representative NV-FF of the merged latch and sensing circuit structure.

Simulation of the Margins in Single Flux Quantum Circuits Containing π-Shifted Josephson Junctions

Abstract: We designed several single flux quantum (SFQ) flip-flops and logic gates composed of Josephson junctions (JJs) and π-shifted JJs (π-JJs) to quantitatively evaluate effectiveness of introduction of π-JJs into the SFQ logic circuit. One-output flip-flops and logic gates were designed on the basis of the circuit design methodology we built for the SFQ circuit containing π-JJs. The designed flip-flops and logic gates have wide operating margins, the dc-bias margins of larger than ±30%, and device parameter margins of ±18%, though the static power consumption are reduced compared to conventional ones composed of JJs. We found that the difference in the critical current density between JJs and π-JJs does not affect the operating margins of the SFQ flip-flop composed of JJs and π-JJs. We devised a circuit structure of the delay flip-flop with complementary outputs composed of JJs and π-JJs (π-DFFC). The analog circuit simulation shows the dc-bias margin of the π-DFFC is larger than ±33%. These results indicate that the large-scale SFQ logic circuit system can be implemented using the flip-flops and logic gates containing π-JJs.

An SR Flip-Flop based Physical Unclonable Functions for Hardware Security

Abstract: Physical Unclonable Functions (PUFs) have emerged as a promising solution to identify and authenticate Integrated Circuits (ICs). In this paper, we propose a novel NAND-based Set-Reset (SR) Flip-flop (FF) PUF design for security enclosures of the area- and power-constrained Internet-of-Things (IoT) edge node. Such SR-FF based PUF is constructed during a unique race condition that is (normally) avoided due to inconsistency. We have shown, when both inputs (S and R) are logic high (‘1’) and followed by logic zero (‘0’), the outputs Q and $\bar Q$ can settle down to either 0 or 1 or vice-versa depending on statistical delay variations in cross-coupled paths. We incorporate the process variations during SPICE-level simulations to leverage the capability of SR-FF in generating the unique identifier of an IC. Experimental results for 90nm, 45nm, and 32nm process nodes show the robustness of SR-FF PUF responses in terms of uniqueness, randomness, uniformity, and bit(s) biases. Furthermore, we perform physical synthesis to evaluate the applicability of SR FF PUF on five designs from OpenCores in three design corners. The estimated overhead for power, timing, and area in three design corners are negligible.

An Adaptive Single Event Upset (SEU)-Hardened Flip-Flop Design

Abstract: In this paper, a new radiation hardened flip-flop design technique is proposed. The structure provides an possibility that the D-type flip-flop can be configured as an Single Event Upset (SEU) hardened or non-hardened flip-flop in a circuit based on the logic states of the sensitive nodes with RC filtering structure being involved or not, considering speed and reliability. The proposed structure makes itself more widely used in both space, defense applications and high-performance terrestrial applications. Spice simulation results show that the flip-flop has good performance of SEU-hardness and flexibility.

Fluctuating Power Logic: SCA Protection by $V_{DD}$ Randomization at the Cell-level

Abstract: In this paper, we propose a novel cell-level side channel countermeasure fluctuating power logic (FPL), which diffuses the correlation between the real power consumption and the fixed data transitions by employing a cascade voltage logic. The countermeasure further acts as a cell-level V DD randomizer, making it a strong candidate for implementing algorithmic countermeasure and exploiting its noise generation capabilities. This proposed scheme is illustrated by a standard flip-flop. HSPICE based simulation results show that the modified flip-flop is resistant against power analysis at the cost of doubled power dissipation. Two illustrative case studies of PRESENT and AES substitutions have been explored. The resistance against Side-Channel Analysis(SCA) is evaluated by the correlation power analysis. The new logic outperforms other counterparts in consideration of both security and cost, which renders it as a practical solution for resource-constrained systems. The proposed cell-level countermeasure can naturally mitigate other SCA such as electromagnetic analysis.

Low Power High Speed 15-Transistor Static True Single Phase Flip Flop

Abstract: In any digital circuit design, Flip Flops are the most common and important building block. The factors affecting the design are the area, power and performance. The 3 parameters must be optimized for an efficient design. The focus is on the power and performance optimization in a time constrained design. There are many techniques to optimize PPA (Power Performance Area) factors. In this paper high speed low power 15-Transistor FF is proposed. The FF is designed in Master-Slave configuration. It is designed using static CMOS and complementary pass transistors logic. The FF is designed avoiding floating internal nodes to reduce dynamic power consumption. The Cadence Virtuoso tool is used for the implementation of the Flip Flop with supply voltage V DD of 1V and clock frequency of 500MHz. The implementation technology used is 45nm. The results of the power dissipation and the delay is compared with Transmission Gate Flip Flops(TGFF), Topologically compressed Flip Flop(TCFF) and Logical structure Reduction Flip Flop (LRFF). Results of the proposed design was found that it is more efficient than the other compared FF designs. In comparison with TCFF, the PDP improvement of the proposed design was 49.298 at 10% switching factor

Voltage level monitoring of an integrated circuit for production test and debug

Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

A Memristor-based Scan Hold Flip-Flop

Abstract: The scan based design-for-testability (DfT) has been widely adopted in modern integrated circuits (ICs) design to facilitate manufacture testing. However, the transitions in scan cells result in much test power consumption during testing. The scan hold flip-flop (SHFF) can insulate the transitions in scan chain from the circuit under test to reduce test power while incurring much area overhead. We propose to solve this problem by adopting a memristor-based D flip-flop (DFF) into SHFF. The new design breaks down the design structure of conventional CMOS scan cells and adopts memristors into SHFF to reduce the number of transistors and hence the chip area. The functionality of the proposed design is verified to be correct by HSPICE simulation. Compared with the conventional SHFF cells, the area overhead is reduced 26.5%

Multi-Threshold CMOS Devices: A Comparative Analysis of Leakage Power and Delay in Digital Circuits for Nano-Scale Technology

Abstract: In today’s technology trend creative and effective design solution is necessary in order to design high performance CMOS VLSI circuits. In nano-scale technology leakage power contributes a large amount of entire power dissipation of a circuit. The main cause of increased leakage power is due to process parameter decrease. Therefore, power dissipation in small devices are now a primary design challenge. Excessive power dissipation can be controlled by reducing supply voltage but that will increase propagation delay. So, we have the dilemma of power and speed in high performance circuit design. A designer must tradeoff between power and speed based on requirement. Multi-threshold CMOS can be an excellent choice to implement in a larger design to achieve most optimum circuit performance. In MTCMOS technology there are low threshold (LVT) CMOS devices & high threshold (HVT) CMOS devices. LVT CMOS can be used where high speed is required while HVT CMOS can be used for low power requirement. In some cases, an optimum design should be a combination of both HVT and LVT. In this paper four widely used D flip flop integrated circuits are taken as examples and analyzed with MTCMOS - LVT & HVT separately. Various performance parameters such as total power, leakage power, propagation delay & leakage power and delay product (PDP) are analyzed. A comparative analysis of power versus delay in four types of D flip flop topologies with MTCMOS are presented afterwards. All the designs are simulated in cadence virtuoso 45nm technology.

An SR Flip-Flop based Physical Unclonable Functions for Hardware Security

Abstract: Physical Unclonable Functions (PUFs) have emerged as a promising solution to identify and authenticate Integrated Circuits (ICs). In this paper, we propose a novel NAND-based Set-Reset (SR) Flip-flop (FF) PUF design for security enclosures of the area- and power-constrained Internet-of-Things (IoT) edge node. Such SR-FF based PUF is constructed during a unique race condition that is (normally) avoided due to inconsistency. We have shown, when both inputs (S and R) are logic high ('1') and followed by logic zero ('0'), the outputs Q and Qbar can settle down to either 0 or 1 or vice-versa depending on statistical delay variations in cross-coupled paths. We incorporate the process variations during SPICE-level simulations to leverage the capability of SR-FF in generating the unique identifier of an IC. Experimental results for 90nm, 45nm, and 32nm process nodes show the robustness of SR-FF PUF responses in terms of uniqueness, randomness, uniformity, and bit(s) biases. Furthermore, we perform physical synthesis to evaluate the applicability of SR FF PUF on five designs from OpenCores in three design corners. The estimated overhead for power, timing, and area in three design corners are negligible.

Low-Power Highly Reliable SET-Induced Dual-Node Upset-Hardened Latch and Flip-Flop

Abstract: It appears that the relentless pursuit of Moore’s law scaling from one generation of process technology to the next increases circuit vulnerability to single-event transient (SET)-induced double-node upset (SEDU). In this paper, we present a novel SEDU-hardened latch. The latch consists of a new 16-transistor (16T) SEDU-hardened storage cell and a C-type output buffer. The latch exhibits 25% lower power consumption, is 81% faster, and also shows 86% lower power-delay product than the existing SEDU-hardened latches. In addition, we present the first SEDU-hardened flip-flop that exhibits negative hold time. The proposed SEDU-hardened flip-flop is 29% faster, consumes 50% lower dynamic power and 25% lower static power, has 45% lower setup time, and uses 27% lower area than the existing partial SEDU-hardened flip-flop.

Double data rate interpolating analog to digital converter technical field

Abstract: A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core; and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and 5 a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

Design of low power SR-flip-flop with on/ off (ONOFIC) implementation

Abstract: Metal oxide semiconductor (MOS) devices are the basic building blocks for the logic circuits. Advancement in technology increases the expectation of customer in electronics. Various challenges face by IC designer during the uses of this Nano-scale technology because no one technology is completely satisfied all requirements. Better performance with minimum power dissipation and high stability is become basic need and low power dissipation is possible when power consumption of VLSI device is low. As the need of small electronics components and devices is increased day by day. There is a rapid growth in industry of electronics in few decades. World and technology are growing at the same speed. Day by day as the demand for small devices increases with high efficiency and result in flip-flop came into existence. These flip-flops have number of applications in electronics like used in communication, computers. As the size of the flip-flops decrease there is a problem of leakage current which prevents us to design a low power circuit. To decrease these leakage currents in the SR flip-flops and made it as a low power flip-flop an approach is used in this paper called as ON/OFF (ONOFIC). This ONOFIC implementation of SR flips decreases the leakage current and in this way our SR flip-flop is low power consuming

Computer architecture for emulating a binary correlithm object flip flop

Abstract: A device configured to emulate a correlithm object flip-flip logic gate comprises a memory and a logic engine. The memory stores a flip-flop logic gate truth table that comprises input logical values, a state input logical value, a set/reset input logical value, and output logical values. These logical values are represented by correlithm objects. The logic engine receives the state input and the set/reset inputs and determines an appropriate output based on a determination of Hamming distances between the inputs and the logical values in the truth table.

Flip-flop State Driven Clock Gating: Concept, Design, and Methodology

Abstract: Flip-flop's input data toggling based clock gating is one of the most widely used clock gating methods, in which one critical and inherent limitation is the sharp increase of gating logic as more flip-flops are gating. In this work, we propose a new clock gating method to overcome this limitation. Precisely, (1) we analyze the resources of gating logic in the input data toggling based clock gating, from which an ineffectiveness in resource utilization is observed and we propose a new clock gating technique called flip-flop state driven clock gating which completely eliminates the essential and expensive component of XOR gates for detecting input toggling of flip-flops; (2) we provide the supporting logic circuitry of our proposed XOR-free clock gating, confirming its safe applicability through a comprehensive timing analysis; (3) we propose, based on the flip-flops' state profile, a clock gating methodology that seamlessly combines our flip-flop state based clock gating with the toggling based clock gating. Through experiments with benchmark circuits, it is confirmed that our clock gating method is very effective in reducing power, which otherwise the toggling based clock gating shall miss the power saving opportunity, while meeting all timing constraints.

Automatic Conversion from Flip-flop to 3-phase Latch-based Designs.

Abstract: Latch-based designs have many benefits over their flip-flop based counterparts but have limited use partially because most RTL specifications are flop-centric and automatic conversion of FF to latch-based designs is challenging. Conventional conversion algorithms target master-slave latch-based designs with two non-overlapping clocks. This paper presents a novel automated design flow that converts flip-flop to 3-phase latch-based designs. The resulting circuits have the same performance as the master-slave based designs but require significantly less latches. Our experimental results demonstrate the potential for savings in the number of latches (21.3%), area (5.8%), and power (16.3%) on a variety of ISCAS, CEP, and CPU benchmark circuits, compared to the master-slave conversions.

Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes

Abstract: A pulsed-DICE latch design that operates similar to an edge-triggered flip-flop with improved SER performance is presented. Design was implemented along with conventional D-flip-flop and conventional DICE flip-flop in 16 nm and 7 nm bulk FinFET CMOS processes. The pulsed-DICE latch did not show any upsets with alpha particles and neutrons and has more than 2 orders of magnitude improvement in heavy-ion cross-section compared to conventional D-FF. The proposed design benefits from 60% higher speed than the conventional DICE flip-flop design along with significantly lower area and power penalties.

Design of Sequential Circuit Using Data Driven Clock Gating and Multibit Flip-Flop Integration

Abstract: Flip-flops are one of the most important and basic block of any digital circuits. The power being on the major factor in designing of the digital circuits has to be optimized to improve the performance of the circuit. There are many low power methods available to reduce the power dissipation. the idea here is to combine the low power techniques to order to obtain further power reduction design. The Objectives of the project are to design a high speed, low power D - flip-flop and to design the multibit flip flop and to design data driven clock gating circuit and to combine two different power reduction technique i.e data driven clock gating and multi flip-flop technique and to apply the combined techniques into a sequential design and measure the power utilization and speed of the circuit and contrast it and the conventional design. The LRFF is used to implement the low power techniques. The cadence virtuoso tool is used for the implementation of the circuit and the technology used is 45nm. The results of the power dissipation and is compared with that of the conventional D Flip-flop, the improvement was found to be 36.5% with clock gating of logic structure reduction Flip-flop, and 52.714% with integration of logic structure reduction Flip-flop. Results obtained shows the impact of combining the low power techniques and this basic reduction can reduce the overall power dissipation in the digital circuits.

Stochastic Circuit Design of Image Contrast Stretching

Abstract: Stochastic computing (SC) is a promising technology with low power consumption, low area cost and high fault tolerance for hardware design. This paper presents the circuit design of image contrast stretching by using the SC technique. The proposed architecture requires only one random number generator by exploiting the positive correlation between bit-streams and integrates the JK flip flop into the new circuit for image contrast stretching. Synthesized results of hardware implementation indicate there are reductions of 44%, 42% and 45% in area, delay and power consumption over the existing Markov-based finite state machine (FSM) design.

Self-gating flip-flop

Abstract: A self-gating flip-flop circuit includes a flip-flop circuit and a clock circuit. The flip-flop circuit includes a clock input. The clock circuit is coupled to the clock input. The clock circuit includes a latch circuit, a reset circuit, and a gate circuit. The reset circuit is coupled to the latch circuit. The gate circuit is coupled to the latch circuit and the clock input.

Design of CMOS Based D Flip-Flop with Different Low Power Techniques

Abstract: This paper shows designs of CMOS based D flip flop circuits using the forced nMOS stacking, LCNT (leakage controlled nMOS transistor), and LECTOR (leakage controlled transistor). Flip-Flops are the critical foundation stones of all modern digital circuits. This paper reports design and analysis of various low power techniques. The simulations have been carried out in SPICE based on TSMC 180nm CMOS technology. Conventional D flip-flop using the primary CMOS inverters is used as a reference circuit. A comparison based on power consumption, propagation time delay, and PDP is carried out. The conventional design shows the power dissipation of 470.811pW with a supply of 1.8V. The LCNT and LECTOR technique shows the power dissipation of 471.216pW and 350.841pW respectively. The proposed forced nMOS stacking technique shows the power dissipation of 149.308pW which gave 68.28% reduction in power consumption as compared to the conventional circuit. The analysis gives us a deep insight about the performance of the circuit when subjected to different techniques, thereby improving certain aspects of the circuit with a slight trade-off in time delay in few instances.