Showing papers on "Flip-flop published in 2021"

High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register

Abstract: Multiple-valued logic (MVL) shows considerable advantages over binary logic in certain applications because of the increased informational content of its signals, and hence reduction in interconnects. Flip-flops (FFs) are the basic elements of many systems and are widely used in microprocessors due to their high performance. This article presents two spintronic ternary retention FFs, and a nonvolatile universal ternary shift register (NUTSR) based on gate-all-around carbon nanotube field-effect transistors (GAA-CNTFETs) and nonvolatile magnetic tunnel junction (MTJ). In the proposed input-aware ternary retention FF circuit, power consumption is significantly reduced by adding a magnitude comparator (MC) circuit and preventing duplicate data transfer to MTJs. Simulation results indicate that our design offers at least 22%, 40%, and 15% reductions in power consumption, backup time, and restore energy, respectively. Moreover, it eliminates the risk of data loss in the event of a sudden power outage.

High-Performance Radiation-Hardened Spintronic Retention Latch and Flip-Flop for Highly Reliable Processors

Abstract: Radiation vulnerability and high power density are critical challenges in modern CMOS processors. Spin-based devices like magnetic tunnel junction (MTJ) are among the promising alternatives for addressing these challenges thanks to their fascinating properties such as radiation immunity, non-volatility, high endurance, and compatibility with the CMOS fabrication process. Utilizing the fascinating non-volatile property of the MTJ device, a high-performance, and energy-efficient soft error immune retention latch, and a high-reliable non-volatile flip-flop (FF) are proposed in this paper. Thanks to the single event upset (SEU) immunity, the proposed circuits are applicable in designing highly reliable processors, especially in applications like aerospace systems, where immunity to radiation induced soft errors is very critical. Because of the innovative design of the proposed approach, the MTJ switching delay does not affect the performance of the proposed latch. The simulation results indicate that the proposed latch offers lower delay, power consumption, and power delay product (PDP) than the state-of-the-art designs. The results of the comprehensive Monte-Carlo simulations also demonstrate that the proposed approach is more robust to process, voltage, and temperature variations as compared to their previous counterparts. This is because our designs do not use a pre-charge sense amplifier (PCSA) to read the data stored in the MTJs, and hence, the proposed designs have lower error rates. Furthermore, the transient impact of the particle strikes on the internal nodes is not transferred to the output node of the proposed circuits. The proposed design also has a significantly shorter output recovery time compared to its state-of-the-art counterparts.

A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop

Abstract: Double-edge triggered flip-flops (DETFF) project a solution to clock power reduction by lowering the clock frequency and maintains the same data rate. Hence, they are appropriate to be used as shift registers. This paper has reviewed several earlier designs of double-edge triggered flip-flops and presented an 8-bit low power shift register by using a newly designed DETFF. The major contribution of this work takes advantage of two parallel data paths that work in opposite phases of the single clock without an inverted input trigger. The proposed shift register design is realized using a typical 90-nm CMOS process. The post-layout results show that the proposed shift register reduces the power consumption by at least 17.2%.

VLSI implementation of Wave Shaping Diode based Adiabatic Logic (WSDAL)

Abstract: This paper presents a new architecture of energy recycling for low power applications. The reported design is based on the ultra-low-power diode Based on this concept, adiabatic logic inverter, a s...

Breaking the Limits in Ternary Logic: An Ultra-Efficient Auto-Backup/Restore Nonvolatile Ternary Flip-Flop Using Negative Capacitance CNTFET Technology

Abstract: Despite the advantages of ternary logic, it has suffered from excessive transistor count and limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) based on negative capacitance carbon nanotube field-effect transistors (NC-CNTFETs). By harnessing the negative differential resistance effect in NC-CNTFETs, the proposed design is similar to a conventional volatile binary FF regarding the number of transistors and control signals. During a scheduled power gating or a sudden power outage, the proposed ternary FF benefits from an auto-backup/auto-restore capability without employing any additional transistors, nonvolatile devices, or control signals. This leads to zero device overhead, which is a breakthrough in designing nonvolatile memory circuits. On the other hand, the back-to-back slave latch’s hysteretic behavior provides an extraordinary static noise margin that transcends the noise margin of both conventional ternary and binary latches. The simulation results indicate that eliminating additional backup and restore circuitries provides 43% improvements in transistor count, 59% improvements in power saving and 98% improvements in energy-saving than state-of-the-art binary and ternary FFs. Moreover, the proposed design presents a 1.5 times higher static noise margin than the conventional binary and ternary FFs. Our proposed approach opens new doors in realizing ultra-efficient nonvolatile ternary circuits and systems in neuromorphic applications using ferroelectric-based transistors.

Design of two-dimensional photonic crystal based ultra compact optical RS flip-flop

Abstract: The presented research deals with designing of a new ultra compact all-optical RS flip-flop on a two-dimensional (2-D) hexagonal photonic crystal platform. The flip-flop is designed by using two NOR gates, photonic crystal waveguides, four silicon ring resonators, four input ports and two output ports. The designed flip-flop structure has hexagonal silicon rods in the air host with a lattice constant a of 630 nm. Si rods have a radius of 0.2a and operating waveleangth of 1550 nm. The novel design provides proper distinction between logic 1 and logic 0 at the output by giving 8.7 dB and 4 dB contrast ratio at Q and Qbar output, respectively. Furthermore, uncomplicated structure resulting in small dimension of 28 μm * 28 μm makes it appropriate for optical integrated circuit in optical networks. FDTD method is used to model the proposed structure and simulated using RSoft FullWAVE simulator tool.

YBa $_{2}$ Cu $_{3}$ O $_{7-\delta }$ Single Flux Quantum Flip Flop Directly Written With a Focused Helium Ion Beam

Abstract: Superconducting logic circuits based on low transition temperature ( $T_c$ ) are attractive due to their intrinsic low power consumption and high operating frequency. They have a wide variety of applications (particularly in future computing), but are difficult to use because they require cooling with liquid helium to operate. The current high $T_c$ logic circuit based on YBa $_{2}$ Cu $_{3}$ O $_{7-\delta }$ (YBCO) already has the ability to operate at a temperature above 4 K. However, this material is difficult to integrate into large-scale circuits by the traditional YBCO junction fabrication process. The limits of fabrication methods are the bottleneck stifling this material's potential for integration into logic circuits. As such, in this paper we aim to advance the state of the art in junction fabrication technology. Here we report the demonstration of a high $T_c$ superconducting single flux quantum (SFQ) circuit made by a focused helium ion beam that is easily fabricated and can readily be incorporated into a large-scale integration with nano-scale junctions for future applications. An inductively coupled readout superconducting quantum interference device (SQUID) is employed to reduce the circuit complexity. The circuit parameters and performance are discussed.

A Bypassable Scan Flip-flop for Low Power Testing with Data Retention Capability

Abstract: The power consumption of modern highly complex chips during scan test is significantly higher than the power consumed during functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures of the integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) is proposed for low-power IC test. The proposed flip-flop contains two secondary latches. The output of the “function” secondary latch goes to the following combinational circuits, while the other “shadow” secondary latch is used to shift test vectors during scan test. By gating the output of the function secondary latch, the redundant switching activity in the combinational circuits is eliminated during scan shift, thereby reducing the test power consumption significantly. The suppressed switching activity also leads to lower IR drop across the chip, increasing the chip manufacturing yield. Furthermore, the shadow latch is reused for data retention in the sleep mode while performing power gating, thereby alleviating the area cost of the shadow latch. The proposed BPS-DRFF also eases the hold time sign-off in the test mode due to the elongated clock-to-Q contamination delay that is brought in by the shadow latch. The proposed design is applied to an AES-128 crypto core in a UMC 55-nm low power CMOS technology. Experiment results show that 68.5% power is saved during scan test with the proposed BPS-DRFF, compared to the standard scan retention flip-flop.

Using Universal Nand-nor-inverter Gate to Design D-latch and D Flip-flop in Quantum-dot Cellular Automata Nanotechnology

Abstract: The process of reducing dimensions in CMOS technology and also making digital devices more portable, faces serious challenges such as increasing frequency and reducing power consumption. For this reason, scientists are looking for a solution such as replacing CMOS technology with other technologies including Quantum-dot Cellular Automata (QCA) technology and many researches have designed digital circuits by using QCA technology. Flip-flops are one of the main blocks in most digital circuits. In this paper, a D-type flip-flop (D-FF) is presented in QCA technology that a majority gate has been used in its feedback path to reset. The D-FF is designed by the proposed D Latch which is based on Nand-Nor-Inverter (NNI) and a new inverter gate that the proposed D latch has 24 cells and 0.5 clock cycle latency and 0.02 〖μm〗^2 area. The new inverter gate of the D-FF has output signal with high polarization level and lower area than previous inverters and the NNI gate of the D-FF is a universal gate. One of the applications of D-FFs with reset pin is the use in Phase-frequency detector (PFD). In the proposed scheme, a reset feature has been added to D-FF since the PFD structure can be designed. All of the proposed schemes are evaluated by the QCADesigner software and energy consumption simulations are estimated using QCAPro software for all proposed circuits.

Design and Study of Circuits Using Reversible Logic

Abstract: In VLSI systems design, reversible Logic has gained importance for Reducing power. This paper focuses on designing of sequential circuits and reducing the number of constant inputs - CI and the garbage outputs - GO. Basic reversible gates are used to build sequential circuits. D Flip flop, Latch and RAM cell are developed. All circuits are VHDL coded on Xilinx tool, simulated and verified. Reduction in CI of more than 33 percent and GO of more than 80 percent is achieved. This is achieved by properly reusing the outputs for configuring the constant input of other gates.

Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology

Abstract: In this paper, we have designed and proposed a novel D flip-flop using Carbon Nanotube Field-Effect Transistor (CNTFETs). The proposed flip-flop operates on a True Single Phase Clock (TSPC) and is based on a master-slave TSPC latch in a cascaded configuration. The Proposed flip-flop has less Clock load i.e., only on two transistors. From the simulation results, we have observed that the proposed D flip-flop has less setup time (t Setup ), hold time (t hold ), clock to output propagation delay (t Pc–q ), low clock load and low power consumption as well as low energy value compared to other existing flip-flops. The proposed D flip-flop consumes 99.98%, 99.89%, 36.8%, 99.6% low power and low energy compared to NAND based logic Flip-flop, Transmission gate logic based MUX Flip-flop, C2MOS Flip-flop, TSPC flip-flop respectively. Based on the simulated results, the proposed flip-flop is well suited for low power and energy efficient VLSI Systems.

Design of Area Efficient Shift Register and Scan Flip-Flop based on QCA Technology

Abstract: A growing substitute to the CMOS technology to structure the digital circuits is Quantum-dot Cellular Automata (QCA) Technology. The future nano digital circuits using QCA technology are very advantageous in context to low power consumption, device density, and speed. The standard logic elements in QCA are Majority Gate (MG) and Inverter. This paper presents a 5-input MG based logic circuits. The 3-input MG has some demerits; mainly, it needs more gates to implement complex functions. The high-level synthesis circuits such as multiplexer, shift register, and scan Flip-flops are implemented using the 5-input MG. The proposed circuits are advantages in terms of various circuit parameters such as cell counts, area, and gate count compared to the previous circuits implemented with 3-input MG.

A New Design of D Flip-Flop Using Quantum-Dot Cellular Automata

Abstract: The CMOS technology has reached its physical fundamental limit. Due to the shortcomings in CMOS like the short channel effect, doping fluctuations, leakage current, an extensive research is going on. Though various technologies have been proposed, Quantum-dot cellular automata seems to be more attractive technology. QCA is transistor less. It can replace complementary metal–oxide–semiconductor (CMOS) at nano-scale level. The novel digital technology has the advantages of reduced area, high performance. Quantum dot cellular automata requires the basic components like inverters and majority gates. In this paper three new D-Flip Flop have been proposed. The proposed D flip flops are implemented with three-input majority gate. The D Flip-Flop design shows much improvement in terms of cell count, occupation area and input to output delay. The occupation area of proposed D Flip Flop designs have been reduced to 0.05%, 0.07% and 0.78% as compared to the design given in literature. QCA designer 2.0.3 is used to design, simulate and verify the output the circuits.

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Abstract: To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

Complementary Memresistive Switch Based Realization of Delay and Toggle Flip-Flop

Abstract: In-memory computing architecture is gaining momentum to replace the classical Von Neumann architecture with high computational speed. Memristor is a suitable candidate to implement memory and logic in the same platform for performing in-memory computation for high execution speed and performance. This work addresses flip-flop designs using Complementary Memristive switch (CRS) which shows better results in comparison with the earlier designs implemented using different memristive logic styles. The proposed flip-flops are simulated using SPICE which utilizes less number of execution steps with lower count of memristive elements. The power consumption in proposed Delay flip-flop and Toggle flip-flop using CRS reduced by 46.8% and 51.53% as compared to the MAGIC In-memory design which uses pure memristive elements.

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

Abstract: As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has...

Parallel Gate Operations Fidelity in a Linear Array of Flip-Flop Qubits

Abstract: Quantum computers based on silicon are promising candidates for long term universal quantum computation due to the long coherence times of electron and nuclear spin states. Furthermore, the continuous progress of micro- and nano- electronics, also related to the scaling of Metal-Oxide-Semiconductor (MOS) systems, makes possible to control the displacement of single dopants thus suggesting their exploitation as qubit holders. Flip-flop qubit is a donor based qubit (DQ) where interactions between qubits are achievable for distance up to several hundred nanometers. In this work, a linear array of flip-flop qubits is considered and the unwanted mutual qubit interactions due to the simultaneous application of two one-qubit and two two-qubit gates are included in the quantum gate simulations. In particular, by studying the parallel execution of couples of one-qubit gates, namely Rz(-pi/2) and Rx(-pi/2), and of couples of two-qubit gate, i.e. \sqrt{iSWAP}, a safe inter-qubit distance is found where unwanted qubit interactions are negligible thus leading to parallel gates fidelity up to 99.9%.

A pre-discharging based flip-flop with a negative setup time

Abstract: Described is a pre-discharging based flip-flop having a negative setup time which can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

Designof Efficient Scan Flip-Flop

Abstract: Design For Testability (DFT) is a technique used while designing the Integrated Circuit (IC) to add features to the hardware design which helps in testing the design. Scan insertion is one of the DFT techniques which is used in sequential circuits. It is most popularly used as the testability of the circuit will be much better and the design can be easily tested. Scan insertion involves the insertion of scan flip-flop consisting of a D flip-flop with an extra multiplexer and additional scan input and scan output pins. The addition of extra circuitry increases the area, delay and power consumption which is undesirable. Hence, there is increase in the amount of silicon used and in the test time, which leads to lower profits. In this paper, two novel and efficient Scan flip-flop designs have been implemented consuming less power, area and delay. The two unique Scan flip-flop designs namely Gate Diffusion Input based D flip-flop and modified Transmission Gate based Scan flip-flop have been developed in Cadence Virtuoso. An improvement of 42.12% and 27.38% was observed in speed during functional and test modes respectively. A decrease of 47% and 56.73% was observed in peak-power consumption in functional and test modes respectively.

Clock Gating Flip-Flop using Embedded XoR Circuitry

Abstract: Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior stateof-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.

Area optimized design of tetrad flip-flop using new tetrad value logic gate’s

Abstract: Logic levels in digital systems are predefined voltage and current range and a defined difference in voltage and current value signify binary information’s in digital systems. There are many logic families available to define binary data. In binary logic, there are two logic levels 1 and 0. This paper defines a new tetrad value logic (TVL) which can have four logic levels 0,1,2 and 3. This work presented novel designs of tetrad value logic NOT gate, AND gate and OR gate. With the help of these tetrad logic gates, a tetrad logic Flip-flop has been designed and tested on Tanner Electronic Design Automation (EDA) tool. The proposed tetrad flip-flop is a memory cell of tetrad Value Logic (TVL) which can store Logic 0, Logic 1, Logic 2, and Logic 3 when the input clock is off, and on the positive edge of the input clock, it can change the past stored logic with new input logic. This work discusses the possible application of tetrad logic. Simulation of tetrad logic gates and flip flop performed with help of tanner tool and verifies expected output correctly for all possible test cases. Parameters like Voltage levels, power consumption, noise margin, MOS count, propagation time, fan-out, noise margin, clock frequency, sink, source current, setup and hold time, are analyzed for proposed tetrad logic gates and flip flop. The S-edit 9.0 is used for the schematic design and T-spice 9.0 is used for parameter setting and design technology selection and W-edit 9.0 is used for simulation observation. The obtained results have been compared with other similar work and found better.

High-Speed SET D Flip-Flop Design for Portable Applications

Abstract: For reliability of battery operated and portable applications, VLSI designers are being motivated by three basic goals, viz., minimizing the transistor count, minimizing the power consumption and minimizing them, nm and propagation delay. Flip-flop is the basic building block of a sequential device since it is utilized in designing memory block of any digital circuit. This research paper proposes an edge-triggered flip-flop and its outcomes are compared with the flip-flop, which has minimum number of transistors and very less delay. Proposed design is simulated at various temperature and voltage values at 90, 65 and 32 nm technologies that the proposed circuit works efficiently independent of technology. Proposed latch produces better results in terms of delay and PDP as compared to the existing circuit employing less number of transistors is one beneficial way with the aid of which reduction in parasitic capacitances, chip area, propagation delay and power consumption can be acquired.

A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications

Abstract: A low voltage and low power true-single-phase flip-flop (FF) design using 16-transistor only is proposed. It is adapted from conventional master-slave based design and reduces layout area by using hybrid logic scheme. Optimization measures have resulted in a new FF with better power and area performances. Based on simulation results using the TSMC CMOS 180nm, our design achieves the conventional TGFF design by 67.3% in energy and 30.8% in layout area.