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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


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Patent
10 Sep 1993
TL;DR: An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flipflop, unless the scan signal is also active, in which case the flip flop will return to a clocked status as mentioned in this paper.
Abstract: An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.

10 citations

Patent
Kim Min-Su1
02 Jun 2003
TL;DR: In this article, a flip-flop capable of operating at high speed by reducing a clock-to-output delay is described. But it does not use a NAND gate.
Abstract: Provided is a flip-flop capable of operating at high speed by reducing a clock-to-output delay The flip-flop includes a sense amplifier and a latch circuit The sense amplifier includes a first node and a second node, precharges the first node and the second node with a supply voltage according to a state of a clock signal, or receives and amplifies differential input signals according to the state of the clock signal, so as to output differential output signals to the first node and the second node The latch circuit is connected to the first node and the second node, and detects and latches the differential input signals according to the state of the clock signal and the differential output signals The flip-flop described above does not use a NAND gate, so that a clock-to-output delay can be reduced Therefore, the flip-flop has an advantage of operating at high speed

10 citations

01 May 1980
TL;DR: In this article, a first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was developed, leading to logic gates with propagation delays in the range 130-170 ps.
Abstract: A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.

10 citations

Journal ArticleDOI
TL;DR: A novel clocked optical D flip flop using two dimensional photonic crystals has been proposed using unique alignment of line waveguide and ring resonator structures by varying the dimension of the photonic crystal.

10 citations

Book ChapterDOI
01 Jan 2006
TL;DR: This chapter describes the conventional clocking strategies and circuit techniques, and reviews the state-of-the art clocked storage elements used in modern microprocessors, and addresses some emerging methods aimed at handling incoming challenges in the microprocessor design.
Abstract: Clocking is one of the most critical parts of each processor, often determining its performance and largely impacting its power consumption. The clocking subsystem and clocked storage elements in particular are responsible for an increasingly substantial portion of the circuit design improvements needed to accommodate the continuing scaling trends with each processor generation. This chapter describes the conventional clocking strategies and circuit techniques, and reviews the state-of-the art clocked storage elements used in modern microprocessors. In addition, it addresses some emerging methods aimed at handling incoming challenges in the microprocessor design.

10 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868