Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Differential CMOS edge-triggered flip-flop based on clock racing

Abstract: A differential CMOS edge-triggered flip-flop is proposed that employs a pair of cross-coupled inverters, providing fully static operation. The edge-triggering operation is achieved by a narrow pulse, produced by the clock signal and its inverted delayed version. The proposed flip-flop exhibits significant power savings of up to 25%, when compared with other static differential flip-flop circuits, maintaining its speed advantage for different power supply voltages and data activity rates. It also requires only 12 transistors resulting in a reduced transistor count. Moreover, unlike the existing differential circuits, it has the ability to operate under a reduced swing clock signal, without static power dissipation.

Method and apparatus of retaining maximum speed of flip-flop metastability based random number generators

Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.

State retention circuit for radiation hardened flip flop

Abstract: A state retention apparatus for a radiation hardened flip flop for protecting the logic circuitry from radiation induced photocurrents. During periods of transient ionizing pulses of a predetermined magnitude, a switching function is performed to protect the logic state of the flip-flop and after the transients have decayed below a predetermined level, the flip-flop is returned to normal operation.

Clocked set-reset flip-flop

Abstract: Successive clock pulses applied to the clock pulse terminals of a flip-flop cause it successively to change state. A set pulse or reset pulse may be applied to the flip-flop concurrently with a clock pulse which tends to place the flip-flop in a state different than the state intended by the set or reset pulse. The present circuit includes means responsive to the set or reset pulse for preventing the clock pulse from having any effect on the flip-flop. The means may comprise a logic gate to which the clock pulses are applied, storage means for priming the gate when charged, and means responsive to a set or reset pulse for discharging the storage means.

Flip-flop circuit

Abstract: A flip-flop circuit of set-reset type comprising complementary MOS transistors. The flip-flop circuit comprises a first CMOS NOR circuit (10) to which set signal (S) is applied, and a second CMOS NOR circuit (12) having same arrangement as the first CMOS NOR circuit and to which reset signal (R) is applied. Set signal (S) is the logical product signal (φ S .f S ) of first set signal (s s ) and second set signal (f s ). Reset signal (R) is the logical product signal (φ R .f R ) of first reset signal (φ R ) and second reset signal (fR). Neither of first set and reset signals (φ S , φ R ) becomes logic "1" simultaneously. Second set and reset signals (f s , f R ) are kept either unchanged during the time period when first set and reset signals (φ S , φ R ) are logic "1" or become logic "1" only during the time period when first set and reset signals (φ S , φ R ) are logic "1". The first NOR circuit (10) comprises first and second transistors (Tr5, Tr4) of first conductivity type connected in series between first power supply terminal and third transistor (Tr2), third and fourth transistors (Tr2, Tr1) of second conductivity type, and a fifth transistor (Tr3) of second conductivity type connected between the node of second and third transistors (Tr4, Tr2) and the second power supply terminal. First set signal (φ S ) is applied to gates of first and fourth transistors and second set signal (f s ) to the gate of third transistor. The second transistor (Tr4) is gate-connected to the fifth transistor (Tr3).