Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Flip-flop circuit

Abstract: PURPOSE:To reduce delay caused by the load of an FF circuit by connecting a gate circuit which controls the output of a master latch circuit and a slave latch circuit which is used only during a test to different output terminals of the master latch circuit respectively. CONSTITUTION:One input terminal of a gate 1 is connected to the output terminal Q of the master latch circuit LAT1 and the data input terminal D of the slave latch circuit LAT2 is connected to the output terminal Q. Further, one input terminal of a gate 3 is connected to the output terminal Q of the circuit LAT2 and a control signal and its inverted signal are inputted to other-terminal sides of the gates 1 and 3 respectively to control the output state of data. Thus, the gate 1 and circuit LAT2 are connected dispersedly to the terminals Q and Q of the circuit LAT1, so the side of the terminal Q of the circuit LAT1 drives only the gate 1 in normal operation. Consequently, the load on the output terminal Q is reduced and the delay due to the load is reduced.

Flip-flop circuit operating on low voltage

Abstract: Disclosed herein is a flip/flop circuit of a master-slave type including master side and slave side latch/hold circuits 1 and 2 each being of an ECL vertical 1-step construction, first and second bias circuits 3 and 4 for biasing current sources Tr's 21 to 24 of these latch/hold circuits 1 and 2 and a control circuit 5 for pull-down controlling these first and second bias circuits 3 and 4 by clock signals. The current sources Tr's 21 to 24 are thus selectively rendered conductive and non-conductive to perform a flip-flop operation on a low power source voltage such as 1V or less.

D-type master-slave flip-flop

Abstract: The bistable circuit comprises a master unit (M) receiving an input variable (D) and producing first intermediate variables (M,NM). A transfer unit (T) contains two logic gates (3,4) with a clock signal connection (CK). This produces second intermediate variables (X,Y) as functions of the input variable and the clock signal, which are fed back to the master unit. A slave unit (E) produces at least one output variable (Q,NQ). One input of logic gate (3) is connected directly to receive the intermediate variable (M), and one input of logic gate (4) is connected via an inverter (5) to receive a complement (I) of the variable (M). The intermediate variables (X,Y) are mutually independent. In the preferred embodiment, each unit, master, transfer, and slave (M,T,E), contains two NAND gates. In the second embodiment the slave unit contains a NAND and a NOR gates, and two additional inverters. In the third embodiment the master unit contains a NAND and a NOR gates, and an additional inverter in one feedback loop. In the fourth embodiment the master unit is as in the third embodiment, and the slave unit as in the second embodiment. In the fifth embodiment the transfer unit contains an additional NOR gate connected to a control input (CN) via an inverter for set or reset. In the sixth embodiment the master and the slave units are with control inputs (CN). In the seventh embodiment the units are as in the preferred embodiment, but all with NOR gates. In the eighth embodiment the balanced circuit is connected for use as a divisor by two circuit, where the intermediate signals (X,Y) are in counter phase with frequency equal to half that of the clock signal.

Dual data rate flip-flop circuit

Abstract: A dual data rate flip-flop circuit for reducing single event upset errors in the flip-flop circuit including two or more latch circuits connected in parallel. The latch circuits each have a clock input, data input, and latch circuit output. The dual data rate flip-flop circuit also includes a C-element, which has a plurality of inputs and a C-element output. The outputs of the latch circuits are provided to inputs of the C-element, and a keeper circuit is connected to the C-element output. An output buffer inverter connects to the C-element output and has an output corresponding to the dual data rate flip-flop circuit output.

Pulsed state retention power gating flip-flop

Abstract: A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal.