Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Single-Event Upsets and Distributions in Radiation-Hardened CMOS Flip-Flop Logic Chains

Abstract: Single-event upsets are studied in digital logic cells in a radiation-hardened CMOS SOI technology. The sensitivity of SEU to different strike locations and hardening approaches is explored using broadbeam and focused beam experiments. Error distributions in chains of logic flip-flops are studied to determine the impact of various cell designs and hardening techniques on upset uniformity.

A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology

Abstract: We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130nm, and 90nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Integrated logic circuit having plural input cells and flip-flop and output cells arranged in a cell block

Abstract: Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

Dual-Edge Triggered T Flip-Flop Structure Using Quantum-Dot Cellular Automata

Abstract: As an emerging nanotechnology, quantum-dot cellular automata (QCA) has the potential to be used for next generation VLSI. Various designs of combinational logic circuits have been proposed for QCA implementation, but sequential circuit design is limited due to the lack of high-performance QCA flip-flops. After an introduction on QCA and dual-edge triggered (DET) flip-flops, a new QCA DET T flip-flop following a pulsed latch scheme is presented. The proposed T flip-flop is simulated using QCADesigner simulator and its logic functionality is verified. The same data throughput of the DET flip-flop can be achieved while operating at half the clock frequency of a single-edge triggered (SET) counterpart. The proposed flip-flop is promising in building QCA sequential circuits with low power and high performance.

State of the art low power (42 mW per flip-flop) 150 GHz+ CML static divider implemented in scaled 0.2 m emitter-width InP DHBTs

Abstract: Recent development efforts in scaling InP DHBT technologies have pushed transistor cutoff frequencies beyond 400 GHz and demonstrated static flip-flop circuits clocking in excess of 150 GHz. Despite the impressive clock rates, obtaining these operating speeds has required an increase in collector current densities that has largely offset the power reductions achieved to date in scaling the emitter area of the devices in these technologies. Further lateral scaling is required to manage thermal concerns and enable logic circuits of greater complexity. Measured results are shown of a static frequency divider realized in a 0.2 m InP/InGaAs/InP DHBT technology that lowers flip-flop power dissipation to 42 mW while clocking at 150 GHz rates. This represents a factor of two improvement in the state of the art power-delay product over previously reported logic circuits operating at >120 GHz clock rates.