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Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.


Papers
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Journal ArticleDOI
TL;DR: A novel low-power high-speed flip-flop called DETNKFF achieves substantial power reduction by incorporating dual edge-triggered operation and eliminating redundant transitions and minimizes latency by reducing the height of transistor stack on the critical path.

9 citations

Patent
23 Dec 2014
TL;DR: In this article, a scan-testable integrated circuit includes first and second flip-flops and a logic circuit, and the logic circuit deactivates a clock signal provided to the third latch, which is a master latch.
Abstract: A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.

9 citations

Journal ArticleDOI
TL;DR: This work proposes the M-hypercube, using a similar topology to design any sequential logic in spatial dimensions, and shows that MN-cells can implement flip-flops and thus can be used as building blocks for sequential logic design in nanodimensions.
Abstract: Techniques for the advanced logic design of nanodevices and nanolCs in spatial dimensions are being formulated to incorporate specific topologies that satisfy certain requirements of nanotechnology. One of these topologies, the hypercube, is currently being considered for the design of a network-based combinational logic implementation in the form of a hypercube extension called the N-hypercube. We propose the M-hypercube, using a similar topology to design any sequential logic in spatial dimensions. To reduce the complexity of the M-hypercube design, two methods, a top-down and a bottom-up, are presented. The former uses sequential machine decomposition methods and the latter uses a new hypercube topology, called the MN-cell. The MN-cell, consisting of two closely coupled 2D hypercubes, an M-hypercube and an N-hypercube, is a 3D hypercube. It is shown that MN-cells can implement flip-flops and thus can be used as building blocks for sequential logic design in nanodimensions. The logic design of a basic computer in nanospace using MN-cells and N-hypercubes is also presented using several examples.

9 citations

Proceedings ArticleDOI
05 Mar 2014
TL;DR: A detailed design and simulation of a simple D flip-flop based sequential logic circuits like shift register, ring counter and modulo n counter circuits for quantum-dot cellular automata are proposed.
Abstract: Quantum-dot Cellular Automata (QCA) is one of the emerging computing paradigms. Its advantages such as smaller size, lower power consumption and faster speed are very attractive. QCA performs highly dense computing that could be realized in a variety of material systems. It is presently being investigated as an alternative to CMOS VLSI. In conventional digital systems the information is transferred from one place to another by means of electrical current, while as QCA cells transfer information by propagating a polarization state. This paper proposes a detailed design and simulation of a simple D flip-flop based sequential logic circuits like shift register, ring counter and modulo n counter circuits for quantum-dot cellular automata. The proposed designs are based on the D-type flip-flop (DFF) device. A QCA binary wire with four clocking zones can be used to implement a DFF. The aim is to maximize the circuit density and focus on a layout that is minimal in its use of cells.

9 citations

Patent
Kou Ebihara1, Kunihiko Kawaguchi1
05 Aug 1992
TL;DR: In this paper, the authors propose to use a flip-flop circuit to receive complementary output signals of the preceding circuit to compensate driving power and decrease the delay of a specific phase.
Abstract: A semiconductor integrated circuit device includes a preceding circuit portion, a flip-flop circuit portion receiving complementary output signals of the preceding circuit portion, for latching data in accordance with the complementary output signals of the preceding circuit portion, and a compensation circuit portion receiving complementary output signals of the flip-flop circuit portion and receiving the complementary output signals of the preceding circuit portion without passing through the flip-flop circuit portion, for compensating driving power and decreasing a delay time of a specific phase. Therefore, the delay time of the semiconductor integrated circuit device can be decreased in one phase (specific phase).

9 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202353
2022107
202135
202046
201962
201868