Flip-flop

About: Flip-flop is a research topic. Over the lifetime, 2543 publications have been published within this topic receiving 20692 citations.

Soft Error Hardened Latch and Its Estimation Method

Abstract: We propose soft error robust latches which have multi storage nodes and present their efficiencies. The key technology of the latch is a feedback loop circuit with a data node and four gates. We also discuss a method of soft error estimation in robust circuits in this paper. The soft error immunity of this feedback loop circuit is estimated by circuit simulations with two models. The soft error immunity of the latch is estimated by device simulation more accurately. By these precise simulations, the latch is proven to be highly tolerant to soft errors. In addition, the latch protects from not only retention data upset but also transient noise releasing. The latch provides high immunity against all soft error problems with a simple circuit. It is easy to apply the latch technique to various latches, such as single latches, scan latches, and flip-flops.

Timed one-shot active termination device

Abstract: A circuit for driving GTL-type buses actively drives a bus trace towards a first reference voltage when a signal in a first voltage state is detected at its input and actively drives the bus trace towards a second reference voltage for a selected period when the signal at its input transitions from the first voltage state to a second voltage state. The circuit includes a flip-flop for storing the sequential voltage states of the signal, logic for comparing the current voltage state of the signal with a replica of the preceding voltage state of the signal, and first and second transistors of complementary conductivity types, for driving the bus trace to first or second reference voltages, respectively, when activated. The first transistor is turned on when the signal is in the first voltage state. The second transistor is turned on for a period determined by the clock signal driving the flip flop, the type of flip-flop, and, optionally, additional logic gates, when the signal transitions from the first voltage state to the second voltage state.

Signal transmission circuit using transformer - has bistable flip=flop whose input is coupled to HF oscillator and output to buffer store

Abstract: The circuit is intended for potential separated transmission of digital and analogue signals. It uses for this purpose a transformer whose secondary incorporates a semiconductor rectifier bridge. A bistable flip-flop (1) has its input connected to a high frequency oscillator (2), and its output to a buffer store (3). The output of the buffer store is coupled to the transformer (6) primary. the analog or digital signal to be transmitted is fed to the operating voltage input (4) of the buffer store (3). The circuit is particularly applicable to the control of transistor setting elements in such manner that control signals from a logic circuit are transmitted to a power transistor with its base at floating potential.

Phase-frequency detector in QCA nanotechnology using novel flip-flop with reset terminal

Abstract: Today, due to the impossibility of further reducing the dimensions, electronic devices are faced with fundamental challenges in parameters such as speed, frequency, and power consumption for CMOS technology circuit. One solution is to replace CMOS technology with other technologies such as Quantum-dot Cellular Automata (QCA) technology. Extensive researches have been done for design digital circuits in QCA technology. Phase-frequency detector (PFD) is one of the main blocks in electrical and communication systems. In this paper, a structure is presented for a PFD in QCA technology for the first time. In the proposed structure, a D flip-flop (D-FF) with reset ability based on a new inverter gate is used. The new inverter gate of this D-FF compared to previous inverters, has output signal with high polarization level. Also, the proposed PFD has 199 cells, 0.22 μm2 occupied area and two clock cycles latency that is smaller compared with PFD which is designed with the conventional inverter.

Inspection facilitation design method for route delay fault and inspection system generation method

Abstract: PROBLEM TO BE SOLVED: To provide an inspection facilitation design method for a route delay fault, which can obtain a high fault detection rate without considerably increasing area overhead. SOLUTION: The unprocessed route delay fault which is given in an integrated circuit is selected (S11). An initial pattern is generated for the selected route delay fault (S12), and logic values which are set in respective scan flip flops are stored (S13). A transition pattern is generated for the selected route delay fault (S14). It is judged whether the scan flip flop where the logic value is contradicted between the initial pattern and the transition pattern exists or not (S15). A D latch is inserted into the output signal line of the scan flip flop whose logic value is contradicted (S16). The contradiction of the logic value is dissolved by the D latch and the inspection of the route delay fault becomes easy.